Unleashing the 1.6T Ecosystem: Alphawave Semi’s 200G Interconnect Technologies for Powering AI Data Infrastructure

Unleashing the 1.6T Ecosystem: Alphawave Semi’s 200G Interconnect Technologies for Powering AI Data Infrastructure
by Kalar Rajendiran on 12-19-2023 at 6:00 am

Alphawave Semi 224G SerDes 1st TestChip

In the rapidly evolving landscape of artificial intelligence (AI) and data-intensive applications, the demand for high-performance interconnect technologies has never been more critical. Even the 100G Interconnect is already not fast enough for infrastructure applications. AI applications, with their massive datasets… Read More


Synopsys 224G SerDes IP’s Extensive Ecosystem Interoperability

Synopsys 224G SerDes IP’s Extensive Ecosystem Interoperability
by Kalar Rajendiran on 11-27-2023 at 6:00 am

Synopsys 224G SerDes IP InterOp Multiple Tradeshows

Hyperscale data centers are evolving rapidly to meet the demands of high-bandwidth, low-latency applications, ranging from AI and high-performance computing (HPC) to telecommunications and 4K video streaming. The increasing need for faster data transfer rates has prompted a scaling of Ethernet from 51Tb/s to 100Tb/s. Numerous… Read More


Webinar: How 100G/200G Electro-Optical Interfaces Enable Low Power, Low Latency Datacenters

Webinar: How 100G/200G Electro-Optical Interfaces Enable Low Power, Low Latency Datacenters
by Admin on 08-22-2023 at 3:21 pm

Synopsys Webinar | Tuesday, September 19, 2023| 10:00 – 11:00 a.m. Pacific

As the demand for higher data rates, reduced power consumption and minimized latency grows, electrical copper interconnects are becoming an ever-increasing arduous and impractical approach with significant insertion and power losses, and

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Podcast EP169: How Are the Standards for the Terabit Era Defined?

Podcast EP169: How Are the Standards for the Terabit Era Defined?
by Daniel Nenni on 06-30-2023 at 10:00 am

Dan is joined by Priyank Shukla of Synopsys and Kent Lusted of Intel.

Priyank Shukla is a Sr. Staff Product Manager for the Synopsys High-Speed SerDes IP portfolio. He has broad experience in analog, mixed-signal design with strong focus on high performance compute, mobile and automotive SoCs.

Kent Lusted is a Principal Engineer… Read More


Driving the Future of HPC Through 224G Ethernet IP

Driving the Future of HPC Through 224G Ethernet IP
by Kalar Rajendiran on 05-23-2023 at 10:00 am

Advanced DSP Implementations

The need for speed is a never-ending story when it comes to data communications. Currently there are a number of trends such as cloud computing, artificial intelligence, Internet of Things (IoT), multimedia applications and consumer expectations driving this demand. All of these trends are accelerating the growth in high-performance-computing… Read More


Alphawave Semi Showcases 3nm Connectivity Solutions and Chiplet-Enabled Platforms for High Performance Data Center Applications

Alphawave Semi Showcases 3nm Connectivity Solutions and Chiplet-Enabled Platforms for High Performance Data Center Applications
by Daniel Nenni on 05-04-2023 at 6:00 am

Alphawave Semi 3nm Eye Diagram

There were quite a few announcements at the TSMC Technical Symposium last week but the most important, in my opinion, were based on TSMC N3 tape-outs. Not only is N3 the leading 3nm process it is the only one in mass production which is why all of the top tier semiconductor companies are using it. TSMC N3 will be the most successful node… Read More


Mitigating the Effects of DFE Error Propagation on High-Speed SerDes Links

Mitigating the Effects of DFE Error Propagation on High-Speed SerDes Links
by Kalar Rajendiran on 04-18-2023 at 10:00 am

Pre and Post FEC BER as FEC Matrix size Reduces

As digital transmission speeds increase, designers use various techniques to improve the signal-to-noise ratio at the receiver output. One such technique is the Decision Feedback Equalizer (DFE) scheme, commonly used in high-speed Serializer-Deserializer (SerDes) circuits to mitigate the effects of channel noise and … Read More


Podcast EP141: The Role of Synopsys High-Speed SerDes for Future Ethernet Applications

Podcast EP141: The Role of Synopsys High-Speed SerDes for Future Ethernet Applications
by Daniel Nenni on 01-27-2023 at 10:00 am

Dan is joined by Priyank Shukla, Staff Product Manager for the Synopsys High Speed SerDes IP portfolio. He has broad experience in analog, mixed-signal design with strong focus on high performance compute, mobile and automotive SoCs and he has a US patent on low power RTC design.

Dan explores the use of high-speed SerDes with Priyank.… Read More


Integration Methodology of High-End SerDes IP into FPGAs

Integration Methodology of High-End SerDes IP into FPGAs
by Kalar Rajendiran on 11-29-2022 at 6:00 am

AlphaCORE100 Multi Standard SerDes

Over the last couple of decades, the electronics communications industry has been a significant driver behind the growth of the FPGA market and continues on. A major reason behind this is the many different high-speed interfaces built into FPGAs to support a variety of communications standards/protocols. The underlying input-output… Read More


Integrating High Speed IP at 5nm

Integrating High Speed IP at 5nm
by Pavan Patel on 11-10-2022 at 6:00 am

Figure 1

Introduction:

The advancements in deep submicron technology and adding multiple functionalities to reduce costs combined with scaling existing operations means that SoC designs become ever more complex. The biggest driving factors to go below the 16nm process node are the decrease in power and the increase in performance … Read More