Designing SerDes Channels for Protocol Compliance

Designing SerDes Channels for Protocol Compliance
by Admin on 08-18-2020 at 10:00 am

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Register For This Web Seminar

Online – Aug 18, 2020
10:00 AM – 11:00 AM Asia/Singapore
Online – Aug 18, 2020
2:00 PM – 3:00 PM Europe/London
Online – Aug 18, 2020
2:00 PM – 3:00 PM US/Eastern

Overview

Multi-gigabit serial channels present some of the most stringent

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High-Speed SerDes PHY IP for Up to 800G Hyperscale Data Centers

High-Speed SerDes PHY IP for Up to 800G Hyperscale Data Centers
by admin on 08-04-2020 at 10:00 am

If you are designing high-performance computing and networking SoCs for hyperscale data centers, then you require IP that enables large amounts of data to travel at very fast rates. Whether the IP is for true long reach or very short-reach die-to-die connectivity in multi-chip modules (MCMs), you must consider several essential
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High Speed SerDes Design and Simulation Webinar Replay from Mentor

High Speed SerDes Design and Simulation Webinar Replay from Mentor
by Tom Simon on 05-14-2020 at 10:00 am

Mentor SerDes Simulation

Over the years SerDes (serializer/deserializer) based connections have proliferated into just about every connection within and among computing systems. Years ago, parallel interfaces were the most common method of moving data, but issues of signal integrity, synchronization and power simply became too much for the required… Read More


Signal Channel Design and Simulation for Silicon Interposer Packaging on High-Speed SerDes

Signal Channel Design and Simulation for Silicon Interposer Packaging on High-Speed SerDes
by Mike Gianfagna on 02-04-2020 at 10:00 am

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This year is the 25th anniversary for DesignCon.  The show has changed a lot over the years. Today, it’s a vibrant showcase of all aspects of advanced product design – from ICs to boards to systems. The show floor reflects the diverse ecosystem. If you missed it this year, definitely plan to go next year.

The DesignCon technical program… Read More


#56thDAC SerDes, Analog and RISC-V sessions

#56thDAC SerDes, Analog and RISC-V sessions
by Eric Esteve on 06-14-2019 at 5:00 am

The good news is that the next five DAC events will take place in Moscone Center in San Francisco! If going to Las Vegas from the Bay area is an easy trip, coming from Europe to Las Vegas makes it a 24+hours journey… One obvious consequence was the poor attendance to the exhibition floor. But let’s be positive and notice that the number… Read More


Monday DAC IP Session “PAM 4 Enable 112G SerDes”

Monday DAC IP Session “PAM 4 Enable 112G SerDes”
by Eric Esteve on 05-24-2019 at 1:00 pm

This session will open the DAC IP Track at 10:30 on Monday “How PAM4 and DSP Enable 112G SerDes Design” in Room N264. I am very proud to chair this invited paper session, as it addresses one of the key pieces of design, enabling to exchange data flow at the highest possible data rate. It can be between two chips on the same board, we talk … Read More


eSilicon Bucking the Trend at OFC with 7nm SerDes

eSilicon Bucking the Trend at OFC with 7nm SerDes
by Daniel Nenni on 03-11-2019 at 8:00 am

A recent press release from eSilicon caught my eye. The company has been touting their 7nm SerDes quite a bit lately – reach, power, flexibility, things like that. While those capabilities are important, any high-performance chip needs to work in the context of the system, which usually contains technology from multiple sources.… Read More


PCIe 5.0 Jumps to the Fore in 2019

PCIe 5.0 Jumps to the Fore in 2019
by Tom Simon on 03-06-2019 at 12:00 pm

2019 will be a big year for PCIe. With the approval of version 0.9 of the Base Layer for PCIe 5.0, implementers have a solid foundation to begin working on designs. PCIe 4.0 was introduced in 2017, before that the previous PCIe 3.0 was introduced in 2010 – ages ago in this industry. In fact, 5.0 is so close on the heels of 4.0, many products… Read More


eSilicon Expands Expertise in 7nm

eSilicon Expands Expertise in 7nm
by Tom Simon on 02-26-2019 at 12:00 pm

At SemiWiki we usually don’t write about the press releases we are sent. However, a recent press release by eSilicon caught my eye and prompted me to call Mike Gianfagna, eSilicon Vice President of Marketing. The press release is not just about one thing, rather it focuses on a number of interesting things that together show their… Read More


56G and 112G SerDes Where the rubber meets the road

56G and 112G SerDes Where the rubber meets the road
by Tom Simon on 12-11-2018 at 12:00 pm

No matter how high the processing capability of a chip, its overall performance is limited by IO speed. This is very similar to a car with low performance tires, a powerful engine will not be able to transfer its energy to the ground effectively. There is quite literally a race going on between core processing and IO speeds for transferring… Read More