Webinar: Reduce Gate-level Simulation Bring-up Time with Semi-formal X Verification

Webinar: Reduce Gate-level Simulation Bring-up Time with Semi-formal X Verification
by Admin on 03-07-2024 at 3:13 pm

Gate-level simulations (GLS) are a crucial step in the verification of an ASIC/FPGA. GLS is used for verifying power-up, reset operation, timing, multi-cycle paths, and power estimation. However, GLS can be a bottleneck in the project cycle due to its complexity. The nature of a GLS can cause simulations to run much longer than

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CEO Interview: Larry Zu of Sarcina Technology

CEO Interview: Larry Zu of Sarcina Technology
by Daniel Nenni on 03-01-2024 at 6:00 am

Larry Zu Photo 091516

Larry has grown Sarcina from designing semiconductor packages for a few small companies, to doing package designs for top semiconductor companies around the world. From 2014 to 2018, Larry led the expansion of Sarcina beyond package design into final test and wafer sort hardware and software development.

Larry is a semiconductor… Read More


Transformative Year for Sondrel

Transformative Year for Sondrel
by Daniel Nenni on 01-18-2024 at 6:00 am

Happy,New,Year,2023,,Keep,Fighting,Together,,Silhouette,Of,2023

This is our third year working with Sondrel and it has been a great experience. I have always been fascinated with the ASIC business and put a full chapter about it in our first book “Fabless: The Transformation of the Semiconductor industry.” Companies like Sondrel enabled our move to the fabless model and now they … Read More


Webinar: RTL-to-GDSII Flow for ASIC Design Using Cadence Tools

Webinar: RTL-to-GDSII Flow for ASIC Design Using Cadence Tools
by Admin on 11-28-2023 at 4:46 pm

Would you like to know how to design a complete chip using the RTL-to-GDSII Flow?

In this free technical Training Webinar with Application Engineer Sai Srinivas Pamula, we’ll teach you the essential steps in the RTL-to-GDSII design flow using a wide variety of industry-leading Cadence tools—such as the Xcelium Logic Simulator,… Read More


Webinar: Latest Innovations and Updates in ASICs with Efabless!

Webinar: Latest Innovations and Updates in ASICs with Efabless!
by Admin on 11-15-2023 at 3:48 pm

Description

In this webinar Jeff DiCorpo & Matt Venn will delve into the latest ASIC developments, including the game-changing OpenFrame – a new Caravel version expanding your design possibilities by 50%.

Topics Include:

– OpenFrame – a new version of Caravel that gives 50% more area

– GPIO configuration… Read More


Uniquely Understanding Challenges of Chip Design and Verification

Uniquely Understanding Challenges of Chip Design and Verification
by Daniel Nenni on 11-14-2023 at 6:00 am

Jean Marie Brunet (1)

Jean-Marie Brunet is Vice President and General Manager of Siemens Hardware-Assisted Verification. He and I spoke recently about how different his hardware group is from the rest of the software-centric EDA product space and why a hardware-oriented EDA vendor like Siemens fully understands the challenges of the chip design… Read More


Interface IP in 2022: 22% YoY growth still data-centric driven

Interface IP in 2022: 22% YoY growth still data-centric driven
by Eric Esteve on 09-04-2023 at 10:00 am

IF 2018 2027no$

We have shown in the “Design IP Report” 2022 that the market share of the wired Interface IP category is a growing part of the total IP, and that this trend is confirmed year after year. The interface IP category has moved from 18% share in 2017 to 25% in 2022.

During the 2010-decade, smartphone was the strong driver for the IP industry,… Read More


Using Linting to Write Error-Free Testbench Code

Using Linting to Write Error-Free Testbench Code
by Daniel Nenni on 08-23-2023 at 10:00 am

AMIQ EDA Design and Verification

In my job, I have the privilege to talk to hundreds of interesting companies in many areas of semiconductor development. One of the most fun things for me is interviewing customers—hands-on users—of specific electronic design (EDA) tools and chip technologies. Cristian Amitroaie, CEO of AMIQ EDA, has been very helpful in introducing… Read More


Webinar: Comprehensive Static Verification for FPGA and ASIC RTL Designers

Webinar: Comprehensive Static Verification for FPGA and ASIC RTL Designers
by Admin on 06-20-2023 at 4:18 pm

As designs get increasingly complex, design teams are looking to find bugs earlier, to reduce rework and shorten time-to-market. The ultimate “shift left” is to put easy-to-use static verification in the hands of RTL designers to eliminate bugs at their source.

This webinar covers comprehensive static verification capabilities… Read More


Siemens EDA on Managing Verification Complexity

Siemens EDA on Managing Verification Complexity
by Bernard Murphy on 04-13-2023 at 6:00 am

2023 DVCon Harry Foster

Harry Foster is Chief Scientist in Verification at Siemens EDA and has held roles in the DAC Executive Committee over multiple years. He gave a lunchtime talk at DVCon on the verification complexity topic. He is an accomplished speaker and always has a lot of interesting data to share, especially his takeaways from the Wilson Research… Read More