Phillip Stanley-Marbell is the founder and CEO of Signaloid. Up until September 2025, he was a full Professor (Chair of Physical Computation) in the Electrical Engineering Division of the Department of Engineering at the University of Cambridge, where he led the Physical Computation Laboratory. He completed his PhD at Carnegie… Read More
Modern ASIC, SoC, CPU, and GPU development depends on verification processes that detect subtle functional defects before tapeout. SystemVerilog Assertions (SVA) are particularly important because they encode temporal design intent: how signals, states, and transactions must behave across clock cycles. Unlike conventional… Read More
Daniel is joined by Nick Kucharewski Senior Vice President and General Manager for Cisco’s silicon development organization. In this role he is responsible for the end-to-end strategy, cross-functional execution, organization alignment, and product roadmap for Silicon One, Cisco’s uniquely scalable and programmable … Read More
For ASIC design teams, the gap between RTL simulation and first silicon remains one of the most consequential stages of the development cycle. Simulation provides controllability and visibility, but it cannot always reproduce the software workloads, interface behavior, clock interactions, and sustained system activity… Read More
Daniel is joined by Andrew Levy, Vice President of Business Development, IP & ASIC at Alphacore. Andrew leads strategic growth initiatives, customer engagement, technology commercialization, and business development activities for the company’s semiconductor IP, ASIC design services, and advanced microelectronics… Read More
Certus Semiconductor, a trusted leader in custom I/O and ESD solutions, will exhibit at Booth 839 during DAC 2026, July 27–29 in Long Beach. This year, Certus is announcing two new developments in GlobalFoundries 12LP and 12LP+ Processes: one I/O library built for commercial SoC and ASIC design teams, and one library purpose-built… Read More
From Photonic Device Design to Electro-Optical Realization
Co-packaged optics will not scale through photonic device performance alone.
As AI infrastructure pushes bandwidth, power, latency, and reach to new limits, optics is moving closer to the compute engine. The industry is no longer asking only whether a photonic device… Read More
Alchip Technologies reported improved financial results for the first quarter, reflecting continued momentum in advanced artificial intelligence (AI), high-performance computing (HPC), and custom ASIC demand. The company cited stronger customer engagement in leading-edge semiconductor designs and accelerating tape-out… Read More
Geoffrey Rodgers spent most of his career at the intersection of semiconductor technology and go-to-market execution, with a focus on scaling businesses and bringing complex solutions to market. He previously led the Analog Go-To-Market motion at Synopsys following the acquisition of Analog Design Automation and held leadership… Read More
Alchip Technologies has recently reported significant progress in the development of advanced 2nm ASICs, positioning itself as a leader in next-generation semiconductor design for AI and HPC. The announcement highlights Alchip’s efforts to commercialize cutting-edge chip technologies and deliver highly customized … Read More
