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WP_Term Object
(
    [term_id] => 50
    [name] => Events
    [slug] => events
    [term_group] => 0
    [term_taxonomy_id] => 50
    [taxonomy] => category
    [description] => 
    [parent] => 0
    [count] => 1227
    [filter] => raw
    [cat_ID] => 50
    [category_count] => 1227
    [category_description] => 
    [cat_name] => Events
    [category_nicename] => events
    [category_parent] => 0
)
Events
Posted on by Daniel Payne

DVCon Is a Must Attend Event for Design and Verification Engineers

DVCon Is a Must Attend Event for Design and Verification Engineers
by Daniel Payne on 02-03-2020 at 10:00 am
Categories: Events

Learning is a never-ending process for design and verification engineers, so outside of reading SemiWiki you likely want to attend at least a few events per year to keep updated, learn something new, attend a workshop, or even present something that has made your IC project work much better than before. Sure, DAC is always a great event in July, but did you know that at DVCon there are expected to be over 1,000 engineers attending  from March 2-5 in San Jose?

dvcon 2020

I’ve attended DVCon in past years and can tell you that it’s well organized in its 32nd year, and has quite the wide range of activities:

  • Tutorials
  • Luncheons
  • Workshops
  • Receptions
  • Sessions
  • Keynotes
  • Panel Discussions
  • Exhibitors

The General Chair this year is Aparna Dey and she wrote a concise welcome blog on the DVCon site, while her day job is at Cadence working on standards. Speaking of standards, the DVCon event is sponsored by Accellera, the group that promotes so many EDA and semiconductor IP standards activities.

Aparna Dey

Topics on Monday this year include:

AI is all the buzz in our tech world, so the Tuesday Keynote is titled AI for EDA, then presented by Dr. Anirudh Devgan, president of Cadence with past stints at Magma and IBM. Deep learning applied to EDA tools will be discussed.

Anirudh Devgan

Panel sessions should get lively on Wednesday because the first one includes RISC-V and the second one wants to fix what’s broken today, plus you can ask questions to either stump the panelists or get clarification:

You’ll be exhausted trying to attend everything, because there are 42 papers, four tutorials and some 23 poster sessions, 10 workshops and the exhibitors. I’d love to hear your feedback about DVCon this year, so send us your trip reports for sharing with other engineers, or better yet, post your trip report in our Forum.

About DVCon
DVCon is the premier conference for discussion of the functional design and verification of electronic systems. DVCon is sponsored by Accellera Systems Initiative, an independent, not-for-profit organization dedicated to creating design and verification standards required by systems, semiconductor, intellectual property (IP) and electronic design automation (EDA) companies. In response to global interest, in addition to DVCon U.S., Accellera also sponsors events in China, Europe and India. For more information about Accellera, please visit www.accellera.org. For more information about DVCon U.S., please visit www.dvcon.org.

Follow DVCon on Facebook https://www.facebook.com/DVCon or @dvcon_us on Twitter or to comment, please use #dvcon_us.

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