Next significant automotive blog in a string I will be posting (see here for the previous blog).
In the semiconductor world, mixed simulation means mixing logic sim, circuit sim, virtual sim (for software running on the hardware we are designing) along with emulation and FPGA prototyping. While that span may seem all-encompassing,… Read More
The Design and Verification Conference in Europe (DVCon Europe) is the leading European event covering the application of languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits. Sponsored by Accellera Systems Initiative, DVCon Europe… Read More
Authors:
Topic(s): Security
Keywords: security, asset, accellera, sa-edi, IEEE P3164, threat modeling
Abstract: This workshop will demonstrate how to identify assets in intellectual property (IP) in accordance with Accellera’s Security Annotation… Read More
The Accellera UVM Working Group released the IEEE 1800.2-2020-2.0 reference library last year. Since that release, we have been working on a public Github repository to give users enhanced access to the latest bug fixes and to provide bug fix suggestions if they would like. Also, we have developed new, additive features to… Read More
The implementation of Functional Safety standards such as ISO26262 poses challenges during the exchange and integration of functional safety data between different work products and activities, carried out by different teams and/or different layers of the supply chain. Automation with EDA tools
Join Accellera for an informative luncheon focused on the efforts and direction of the Federated Simulation Standard Proposed Working Group (FSS PWG). The luncheon will begin with an update on Accellera working group activity from Chair Lu Dai, followed by the presentation of a Distinguished… Read More
As complexity and the number of clock domains increase in today’s ASIC designs, we are moving towards a hierarchical verification approach. This tutorial covers the proven clock domain crossings (CDC) and Reset Domain Crossing (RDC) schemes, the verification challenges, and the potential… Read More
Introduction: This tutorial explains basic usage of IP-XACT IEEE 1685-2022 for IP re-use and integration flows.
This workshop explains the data model underlying the IP-XACT standard. This SoC… Read More
Efficient Portable Programming – Sequence Development with PSS
Bringing an SoC-level system out of reset into an operational state involves configuring the component subsystems and IPs by properly programming hundreds or thousands of IP registers. Running behavior involves programming… Read More
Semiconductor IP design re-use has enabled the relentless growth in complexity of SoC and chiplet-based systems over the years, and with IP reuse comes many unique challenges. Fabless design companies use IP provided by a vibrant ecosystem of IP suppliers and foundries, plus internal re-use in the quest to get to market more … Read More
