Accellera Systems Initiative has approved Functional Safety Language Standard 1.0 for release, addressing a persistent challenge in semiconductor development: moving safety information reliably between tools, engineering teams, and companies. Announced October 21, the standard establishes a common language and data… Read More
AI was a hot topic at DAC this year. If you attended the event, you’ve already heard about many new tools and systems that aim to improve time to market and quality for advanced semiconductors and systems. I had the pleasure of chairing an Accellera sponsored luncheon panel on Tuesday at DAC that took a different view of AI.
As AI and … Read More
The Design and Verification Conference in Europe (DVCon Europe) is the leading European event covering the application of languages, tools, and intellectual property for the design and verification of electronic systems and integrated circuits. Sponsored by Accellera Systems Initiative, DVCon Europe
The premier conference on the application of languages, tools, methodologies and standards for the design and verification of electronic systems and integrated circuits.
Dear Design, Verification and Validation Community,
It is my great pleasure to welcome you to DVCon India 2026, taking place September 1-3, 2026, at Radisson… Read More
Accellera Systems Initiative invites the design and verification community to join us at the 2026 Design Automation Conference for a focused technical luncheon, “Embracing AI for Advanced Design and Verification,” on Tuesday, July 28, from 12:30–1:45 p.m. at the Long Beach Convention Center, Meeting Room 104C.
Artificial… Read More
At DVCon U.S. 2026, Accellera Systems Initiative reinforces its central role in shaping the future of electronic design and verification through a focused program of workshops, tutorials, and community engagement. As system complexity continues to rise across AI, automotive, HPC, and communications markets, the need for… Read More
SystemC version 1.0 came out in 2000 as a C++ class library for system-level modeling and simulation, and on SemiWiki.com there are some 497 references to the language. I wanted to provide an update in this blog so that engineering teams can become more efficient in using SystemC on their SoC projects, saving time and improving product… Read More
Next significant automotive blog in a string I will be posting (see here for the previous blog).
In the semiconductor world, mixed simulation means mixing logic sim, circuit sim, virtual sim (for software running on the hardware we are designing) along with emulation and FPGA prototyping. While that span may seem all-encompassing,… Read More
Semiconductor IP design re-use has enabled the relentless growth in complexity of SoC and chiplet-based systems over the years, and with IP reuse comes many unique challenges. Fabless design companies use IP provided by a vibrant ecosystem of IP suppliers and foundries, plus internal re-use in the quest to get to market more … Read More
Almost everything that we do in chip design and verification was invented to raise the abstraction above schematics and polygons. Register-transfer-level (RTL) design, functional simulation, logic synthesis, floorplanning, and more fall into this category. Even the notion of binary circuits is an abstraction. Underneath… Read More
