Simulating the Whole Car with Multi-Domain Simulation

Simulating the Whole Car with Multi-Domain Simulation
by Bernard Murphy on 03-21-2024 at 6:00 am

Simulating the Whole Car with Multi-Domain Simulation

Next significant automotive blog in a string I will be posting (see here for the previous blog).

In the semiconductor world, mixed simulation means mixing logic sim, circuit sim, virtual sim (for software running on the hardware we are designing) along with emulation and FPGA prototyping. While that span may seem all-encompassing,… Read More


An Update on IP-XACT standard 2022

An Update on IP-XACT standard 2022
by Daniel Payne on 10-18-2023 at 10:00 am

IP XACT 2022 min

Semiconductor IP design re-use has enabled the relentless growth in complexity of SoC and chiplet-based systems over the years, and with IP reuse comes many unique challenges.  Fabless design companies use IP provided by a vibrant ecosystem of IP suppliers and foundries, plus internal re-use in the quest to get to market more … Read More


The Inconvenient Truth of Clock Domain Crossings

The Inconvenient Truth of Clock Domain Crossings
by Anupam Bakshi on 07-17-2023 at 6:00 am

Figure 3

Almost everything that we do in chip design and verification was invented to raise the abstraction above schematics and polygons. Register-transfer-level (RTL) design, functional simulation, logic synthesis, floorplanning, and more fall into this category. Even the notion of binary circuits is an abstraction. Underneath… Read More


Visit with Agnisys at DAC 2023 in San Francisco July 10-12

Visit with Agnisys at DAC 2023 in San Francisco July 10-12
by Anupam Bakshi on 07-06-2023 at 6:00 am

Accellera Lunch 2023

I’d like to extend an invitation to you and your development team to visit with Agnisys in our booth, #2512, at this week’s Design Automation Conference (DAC) 2023, Monday, July 10-12.

In its 60th year, DAC is recognized as the premier event for the design and design automation of electronic chips to systems, so you can count on team… Read More


Podcast EP137: The International Impact of Accellera’s Work

Podcast EP137: The International Impact of Accellera’s Work
by Daniel Nenni on 01-13-2023 at 10:00 am

Dan is joined by Lu Dai who is currently a Senior Director of Technical Standards at Qualcomm. Previously he was Senior Director of Engineering, leading Qualcomm’s SoC design verification team and front-end methodologies and initiatives. Lu is Chair of Accellera Systems Initiative and serves on the Board of Directors at RISC-V… Read More


Podcast EP96: The History, Reach and Impact of Accellera with Lynn Garibaldi

Podcast EP96: The History, Reach and Impact of Accellera with Lynn Garibaldi
by Daniel Nenni on 07-29-2022 at 10:00 am

Dan is joined by Lynn Garibaldi, Executive Director, Accellera Systems Initiative. Lynn is the recipient of the Accellera 2022 Leadership Award. Dan and Lynn explore the history of Accellera, its beginnings and growth to a multi-standard organization and the impact of DVCon events around the world.

The views, thoughts, and … Read More


Co-Developing IP and SoC Bring Up Firmware with PSS

Co-Developing IP and SoC Bring Up Firmware with PSS
by Kalar Rajendiran on 03-22-2022 at 10:00 am

Creating a Driver

With ever challenging time to market requirements, co-developing IP and firmware is imperative for all system development projects. But that doesn’t make the task any easier. Depending on the complexity of the system being developed, the task gets tougher. For example, different pieces of IP may be the output of various teams… Read More


Breker Verification Systems Unleashes the SystemUVM Initiative to Empower UVM Engineering

Breker Verification Systems Unleashes the SystemUVM Initiative to Empower UVM Engineering
by Daniel Nenni on 02-28-2022 at 6:00 am

SystemUVM Language Characteristics

The much anticipated (virtual) DVCON 2022 is happening this week and functional verification plus UVM is a very hot topic.  Functional Verification Engineers using UVM can enjoy a large number of benefits by synthesizing test content for their testbenches. Abstract, easily composable models, coverage-driven content, deep… Read More


Working with the Unified Power Format

Working with the Unified Power Format
by Daniel Payne on 02-23-2022 at 10:00 am

UPF design flow min

The Accellera organization created the concept of a Unified Power Format (UPF) back in 2006, and by 2007 they shared version 1.0 so that chip designers would have a standard way to communicate the power intentions of IP blocks and full chips. By 2009 the IEEE received the Accellera donation on UPF , reviewed multiple drafts and published… Read More


Accellera at DVCon U.S. 2022 in the Metaverse!

Accellera at DVCon U.S. 2022 in the Metaverse!
by Daniel Nenni on 02-08-2022 at 6:00 am

Gather.Town

The premier verification conference and exhibition is coming up and of course Accellera plays an important role. This year DVCON will again be virtual, which is unfortunate, but I must say as a long time attendee this year’s program really stands out. In fact, there is a new addition that is worth mentioning, it’s the… Read More