Podcast EP96: The History, Reach and Impact of Accellera with Lynn Garibaldi

Podcast EP96: The History, Reach and Impact of Accellera with Lynn Garibaldi
by Daniel Nenni on 07-29-2022 at 10:00 am

Dan is joined by Lynn Garibaldi, Executive Director, Accellera Systems Initiative. Lynn is the recipient of the Accellera 2022 Leadership Award. Dan and Lynn explore the history of Accellera, its beginnings and growth to a multi-standard organization and the impact of DVCon events around the world.

The views, thoughts, and … Read More


Co-Developing IP and SoC Bring Up Firmware with PSS

Co-Developing IP and SoC Bring Up Firmware with PSS
by Kalar Rajendiran on 03-22-2022 at 10:00 am

Creating a Driver

With ever challenging time to market requirements, co-developing IP and firmware is imperative for all system development projects. But that doesn’t make the task any easier. Depending on the complexity of the system being developed, the task gets tougher. For example, different pieces of IP may be the output of various teams… Read More


Breker Verification Systems Unleashes the SystemUVM Initiative to Empower UVM Engineering

Breker Verification Systems Unleashes the SystemUVM Initiative to Empower UVM Engineering
by Daniel Nenni on 02-28-2022 at 6:00 am

SystemUVM Language Characteristics

The much anticipated (virtual) DVCON 2022 is happening this week and functional verification plus UVM is a very hot topic.  Functional Verification Engineers using UVM can enjoy a large number of benefits by synthesizing test content for their testbenches. Abstract, easily composable models, coverage-driven content, deep… Read More


Working with the Unified Power Format

Working with the Unified Power Format
by Daniel Payne on 02-23-2022 at 10:00 am

UPF design flow min

The Accellera organization created the concept of a Unified Power Format (UPF) back in 2006, and by 2007 they shared version 1.0 so that chip designers would have a standard way to communicate the power intentions of IP blocks and full chips. By 2009 the IEEE received the Accellera donation on UPF , reviewed multiple drafts and published… Read More


Accellera at DVCon U.S. 2022 in the Metaverse!

Accellera at DVCon U.S. 2022 in the Metaverse!
by Daniel Nenni on 02-08-2022 at 6:00 am

Gather.Town

The premier verification conference and exhibition is coming up and of course Accellera plays an important role. This year DVCON will again be virtual, which is unfortunate, but I must say as a long time attendee this year’s program really stands out. In fact, there is a new addition that is worth mentioning, it’s the… Read More


Accellera/ESD Alliance Co-Host “The Executive View – Returning to the Office”

Accellera/ESD Alliance Co-Host “The Executive View – Returning to the Office”
by Admin on 08-11-2021 at 12:00 am

On August 11, 2021, Accellera and ESD Alliance will co-host part 2 of a virtual panel to discuss the challenges of transitioning back from remote work to the office.

Register here >

Virtual Event
Wednesday, August 11, 2021 9:00am-10:00am PT

You are invited to our FREE webinar co-hosted by the ESD Alliance and Accellera. A panel… Read More


What’s New with UVM and UVM Checking?

What’s New with UVM and UVM Checking?
by Daniel Nenni on 06-30-2021 at 6:00 am

UVM and UVM Checking

About once a quarter, I touch base with Cristian Amitroaie, CEO and co-founder of AMIQ EDA, to see what’s new with the company, products, and users. Sometimes he surprises me, as he did earlier this year when he mentioned that their tools check about 150 rules for non-standard constructs in SystemVerilog and VHDL. When we talked … Read More


Functional Safety – What and How

Functional Safety – What and How
by Daniel Payne on 05-26-2021 at 10:00 am

Accellera FSWG min

I’ve written before about how the automotive industry adheres to functional safety (FS) as defined in the ISO 26262 standard, along with other SemiWiki bloggers. That standard certainly defines the What part of FS, however it doesn’t mandate how you meet the standard, what tools you should be using, file formats … Read More


CEO Interview: R.K. Patil of Vayavya Labs

CEO Interview: R.K. Patil of Vayavya Labs
by Daniel Nenni on 03-12-2021 at 6:00 am

RK Patil 1

RK has over 25 years of industry experience in the domain of Telecom, Embedded software and Semiconductors. Before co-founding Vayavya, he was a co-founder at Smart Yantra Technologies, where he has held various positions in engineering, marketing and management. At Vayavya RK is responsible for overall management and strategic… Read More