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Leveraging HLS/HLV Flow for ASIC Design Productivity

Leveraging HLS/HLV Flow for ASIC Design Productivity
by Pawan Fangaria on 12-23-2015 at 12:00 pm
Categories: EDA, Mentor, a Siemens Business

Imagine how semiconductor design sizes leapt higher with automation in digital design, which started from standard hardware languages like Verilog and VHDL; analog design automation is still catching up. However, it was not without a significant effort put in moving designers from entering schematics to writing RTL, which… Read More

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Coming to a Workstation Near You: Accellera’s Portable Stimulus Standard

Coming to a Workstation Near You: Accellera’s Portable Stimulus Standard
by Ellie Burns on 11-29-2015 at 7:00 am
Categories: EDA, Mentor, a Siemens Business

Portable Stimulus has become such a popular standards topic of late that I thought it would be good to take a break this month from my low power series to bring you, my valued readers, more information about it from one of my colleagues, Dennis Brophy, who is working to help drive development of this standard within Accellera. I’ll … Read More

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Nine Cost Considerations to Keep IP Relevant –Part2

Nine Cost Considerations to Keep IP Relevant –Part2
by Pawan Fangaria on 10-06-2015 at 7:00 am
Categories: EDA, IP, Semiconductor Services

In the first part of this article I wrote about four types of costs which must be considered when an IP goes through design differentiation, customization, characterization, and selection and evaluation for acquisition. In this part of the article, I will discuss about the other five types of costs which must be considered to enhance… Read More

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Moving up Verification to Scenario Driven Methodology

Moving up Verification to Scenario Driven Methodology
by Pawan Fangaria on 09-11-2015 at 12:00 pm
Categories: Cadence, EDA, Mentor, a Siemens Business

Verification complexity and volume has always been on the rise, taking significant amount of time, human, and compute resources. There are multiple techniques such as simulation, emulation, FPGA prototyping, formal verification, post-silicon testing, and so on which gain prominence in different situations and at different… Read More

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UVM Debugging Made Easy & Productive in Questa

UVM Debugging Made Easy & Productive in Questa
by Pawan Fangaria on 02-11-2015 at 2:00 pm
Categories: EDA

As design complexity and size is increasing, SoC verification has become one of the most difficult and time consuming tasks in the design closure.UVM (Universal Verification Methodology, an accellera initiative) is one of the best verification methodologies that support common language, coherent strategy, clarity and transparency… Read More

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Improving Verification by Combining Emulation with ABV

Improving Verification by Combining Emulation with ABV
by Tom Simon on 10-30-2014 at 4:00 pm
Categories: EDA, Mentor, a Siemens Business

Chip deadlines and the time to achieve sufficient verification coverage run continuously in a tight loop like a dog chasing its tail. Naturally it is exciting when innovative technologies can be combined so that verification can gain an advantage. Software based design simulators have been the mainstay of verification methodologies.… Read More

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Coverage Driven Verification for Analog?

Coverage Driven Verification for Analog?
by Pawan Fangaria on 09-26-2014 at 1:00 am
Categories: EDA, Mentor, a Siemens Business

We know there is a big divide between analog and digital design methodologies, level of automation, validation and verification processes, yet they cannot stay without each other because any complete system on a chip (SoC) demands them to be together. And therefore, there are different methodologies on the floor to combine analog… Read More

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Analog Model Equivalence Checking Accelerates SoC Verification

Analog Model Equivalence Checking Accelerates SoC Verification
by Pawan Fangaria on 08-09-2014 at 7:30 pm
Categories: EDA, STMicroelectronics

In the race to reduce verification time for ever growing sizes of SoCs, various techniques are being adopted at different levels in the design chain, functional verification being of utmost priority. In an analog-digital mixed design, which is the case with most of the SoCs, the Spice simulation of analog components is the limiting… Read More

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With SCE-MI, timing really is everything

With SCE-MI, timing really is everything
by Don Dingee on 09-28-2013 at 11:00 pm
Categories: Aldec, EDA

In one of my favorite movies, Brad Pitt utters the only question that matters in baseball or technology management in the face of uncertainty: “Okay, good. What’s the problem?” Not surprisingly in that scene, as the question circles the table of experts used to doing things the old way, not a single one can answer it correctly in the… Read More

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UVM/SystemVerilog: Verification and Debugging

UVM/SystemVerilog: Verification and Debugging
by Daniel Payne on 05-13-2013 at 2:45 pm
Categories: Aldec, EDA

At DAC in just three weeks you can learn about which EDA vendors are supporting the latest UVM 1.1d (Universal Verification Methodology) standard as defined by Accellera. One of those EDA vendors is Aldec, and they have a 45 minute technical session that you can register for online. Space will fill up quickly, so get signed up sooner… Read More