Coverage Driven Verification for Analog?

Coverage Driven Verification for Analog?
by Pawan Fangaria on 09-26-2014 at 1:00 am

We know there is a big divide between analog and digital design methodologies, level of automation, validation and verification processes, yet they cannot stay without each other because any complete system on a chip (SoC) demands them to be together. And therefore, there are different methodologies on the floor to combine analog… Read More


Analog Model Equivalence Checking Accelerates SoC Verification

Analog Model Equivalence Checking Accelerates SoC Verification
by Pawan Fangaria on 08-09-2014 at 7:30 pm

In the race to reduce verification time for ever growing sizes of SoCs, various techniques are being adopted at different levels in the design chain, functional verification being of utmost priority. In an analog-digital mixed design, which is the case with most of the SoCs, the Spice simulation of analog components is the limiting… Read More


With SCE-MI, timing really is everything

With SCE-MI, timing really is everything
by Don Dingee on 09-28-2013 at 11:00 pm

In one of my favorite movies, Brad Pitt utters the only question that matters in baseball or technology management in the face of uncertainty: “Okay, good. What’s the problem?” Not surprisingly in that scene, as the question circles the table of experts used to doing things the old way, not a single one can answer it correctly in the… Read More


UVM/SystemVerilog: Verification and Debugging

UVM/SystemVerilog: Verification and Debugging
by Daniel Payne on 05-13-2013 at 2:45 pm

At DAC in just three weeks you can learn about which EDA vendors are supporting the latest UVM 1.1d (Universal Verification Methodology) standard as defined by Accellera. One of those EDA vendors is Aldec, and they have a 45 minute technical session that you can register for online. Space will fill up quickly, so get signed up sooner… Read More


ISCUG – Excellent Indian Conference, needs to grow

ISCUG – Excellent Indian Conference, needs to grow
by Pawan Fangaria on 04-21-2013 at 8:05 pm

Promoted by Accellera, SystemC User Groups are in work worldwide; NASCUGin North America, ESCUGin Europe and ISCUG in India. While I was shuffling between my day-to-day work and strategy management course/exams, I received an invitation from my long time colleague, President and CEO of Circuitsutra Technologies, Mr. UmeshRead More


UVM: Lowering the barrier to IP reuse

UVM: Lowering the barrier to IP reuse
by Don Dingee on 02-06-2013 at 2:00 am

One of my acquaintances at Intel must have some of the same viewing habits I do, based on a recent Tweet he sent. He was probably watching “The Men Who Built America” on the History Channel and thinking as I have a lot recently about how the captains of industry managed to drive ideas to monopolies in the late 1800s and early 1900s.

Difference

Read More