WP_Term Object
(
    [term_id] => 16721
    [name] => Vayavya Labs
    [slug] => vayavya-labs
    [term_group] => 0
    [term_taxonomy_id] => 16721
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 2
    [filter] => raw
    [cat_ID] => 16721
    [category_count] => 2
    [category_description] => 
    [cat_name] => Vayavya Labs
    [category_nicename] => vayavya-labs
    [category_parent] => 157
)
            
Vayavya Labs SemiWiki 2
WP_Term Object
(
    [term_id] => 16721
    [name] => Vayavya Labs
    [slug] => vayavya-labs
    [term_group] => 0
    [term_taxonomy_id] => 16721
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 2
    [filter] => raw
    [cat_ID] => 16721
    [category_count] => 2
    [category_description] => 
    [cat_name] => Vayavya Labs
    [category_nicename] => vayavya-labs
    [category_parent] => 157
)

CEO Interview: R.K. Patil of Vayavya Labs

CEO Interview: R.K. Patil of Vayavya Labs
by Daniel Nenni on 03-12-2021 at 6:00 am

RK Patil 1

RK has over 25 years of industry experience in the domain of Telecom, Embedded software and Semiconductors. Before co-founding Vayavya, he was a co-founder at Smart Yantra Technologies, where he has held various positions in engineering, marketing and management. At Vayavya RK is responsible for overall management and strategic decisions related to engineering and business activities.

Vayavya Labs is different from most EDA companies as it provides solutions for software engineers to validate their software for SoCs. How has this journey been so far?

We started Vayavya Labs in 2006, with the single-minded focus of addressing the evolving needs of the embedded software industry and help companies adapt to the different software environments needed for their SoCs.  By then, highly programmable SoCs had already started making inroads into a number of different devices and systems in consumer electronics, automotive, communication and industrial applications. The programmability of these devices and the associated software environments (operating systems and software architectures) had compelled semiconductor companies to build software engineering teams, which often outnumbered the ASIC engineering teams.

Our approach to addressing this problem in the industry was to provide a set of tools and a methodology that would enable code synthesis/generation from a high-level golden specification. This was rather a niche concept and probably a bit ahead in time. We had a number of people appreciating the technology but unwilling to adopt the tool from a small company based out of India.

In 2008, we started an embedded software services unit to help sustain the company and fund our R&D efforts. Over the past decade we have grown steadily, become profitable and have sharpened our focus to address the demanding requirements of SoC verification from a system, software and a hardware perspective.

Today, we are in a rather, unique situation of having the expertise and the solutions to address the hardware and software verification requirements at the architectural, pre-silicon and post-silicon stages of the SoC design flow, to ensure shorter development cycles.

With the number of people working on SoC designs constantly increasing as system companies start developing their own SoCs, what challenges do you envisage Vayavya Labs to solve?

One of the biggest challenges facing designers developing the complex SoCs of today is that there is a need to not only verify the IC designs functionality according to the specification, but also from an end-system context. With shorter time-to-market windows, it is also becoming a necessity for design houses to ensure that the system and SoCs adhere to the many different industry specific standards and requirements prior to taping out. Verification today for a SoC, no longer implies merely hardware verification but also software verification and requires intimate knowledge of embedded systems to ensure system compliance.

As a contributing member of the Accellera committee for portable stimulus (PSS), we have contributed extensively to this standard and our contributions are referred to as Hardware-Software Interfaces (HSI). To enable design companies easily verify their SoC’s from a system software perspective, we have launched an open initiative called OpenHSI™ where designers can leverage from a readymade library of device drivers and middleware stack. We strongly believe that PSS needs to leverage the full potential of HSI /OpenHSI™  in order to realize  software-driven-verification.

At Vayavya Labs, we help companies meet the challenges of verification in three ways namely:

  • We provide virtual platforms by creating models, which can be used to verify the architecture, explore the performance and then subsequently verify the IP/SoC at both pre-silicon and post-silicon stages. In addition, the virtual platforms can also be used to validate the software using emulation.
  • We provide software tools for generating bare metal and operating system specific device drivers, from a hardware-software interface specification, making it easier to validate the hardware-software interface and the SoC functionality from a software perspective.
  • Enable companies to validate their SoCs by building PSS models to automate verification test cases. Additionally, we also help them realize these tests by providing the necessary software drivers and stacks to validate the SoC across all platforms – virtual models, simulation, emulation etc.

In a post-covid era, there is a growing importance of a Digital-Twin. A number of companies are now adopting virtualization for their IPs and SoCs. What solutions does Vayavya Labs provide in this area?

The notion of a digital twin becomes very pertinent these days as it provides an alternative for software and hardware design teams, dispersed across the world to rapidly test, debug and refine their systems. Virtualization as the name implies, removes the dependency on physical hardware for the designers. It provides design teams an opportunity to explore the performance requirements early in the design cycle as well as ensure consistency in the hardware and software verification results for common tests, eliminating the potential of misinterpretation between the two teams. In addition to ensuring concurrent development of software & hardware, virtualization also enables design teams to robustly test the hardware-software to mitigate post-silicon issues.

Unfortunately, developing virtual models is quite challenging as it needs varied technical skills such as knowledge about the modeling languages, insights into the hardware architecture, embedded software and domain knowledge.

Vayavya Labs provides two types of solutions to address the need for virtual platforms. The first solution includes providing ready-made  generic modeling libraries to jump-start virtual platform development and software for automatic generation of device drivers. The second type of solution includes custom development services such as developing custom SystemC, QEMU, Simics, SimNow models for IPs and SoC peripherals in addition to custom development of bare metal software, OS bring up, OS port and software device drivers.

Vayavya Labs has been part of the Accelera committee for portable stimulus (PSS) and has contributed significantly in the area of hardware-software interface. There is also an OpenHSI™ initiative, which Vayavya Labs has initiated to promote PSS usage. Can you elaborate more about it?

The benefits of using PSS are significant as it enables design teams to define the test intent through the domain specified language (DSL) in PSS and use it across all platforms such as simulation, FPGAs, emulation etc. It also provides the hardware and software engineers an inherent ability to test the SoC from a system and software perspective. However, one of the biggest impediments to PSS adoption is in realizing the tests defined in the DSL as it requires API’s, device drivers and middleware/protocol stacks to be exercised completely by the software. All this falls in the realm of embedded software, the nuances of which most hardware design engineers are uncomfortable with. Consequently, to promote the usage of PSS across semiconductor companies, Vayavya Labs launched the OpenHSI™  initiative which includes some commonly used API’s, device drivers & middleware stacks for use by engineering teams to jumpstart their system level verification.

Your team has been working on the device driver generator (DDGen) tool for some time now, something which would be of immense value as design companies struggle to verify their SoCs from a system perspective. Can you provide any insights  about it?

Thanks for bringing up this question. Our efforts to develop a software tool (DDGen), which can automatically generate device drivers from a specification, continues to evolve as we keep learning and  adapt continuously to the changing trends in the industry such as safety in automotive, consumer electronics etc. DDGen Tool is now a stable product and is currently in use with a few customers. With the current emphasis on system validation, we expect to have more customers using DDGen.

Our current offering of DDGen, also helps automotive ECU developers  with MCAL automation. The MCAL drivers generated through DDGen can easily be integrated with any AUTOSAR stack provider to enable rapid development of ECU software for automotive applications.

DDGen, in addition to creating device drivers, also plays a vital role in PSS adoption for SoC system level verification as it generates consistent  register access APIs and bare metal drivers to be used by all hardware and software teams.

What does the next 12 months have in store for Vayavya Labs?

We have grown at a modest rate over the past decade, building up the necessary expertise, domain knowledge and credibility with the customers while maintaining profitability. We are now well poised for growth in the automotive, consumer electronics and wireless/5G verticals. We are also continuing to expand our presence in North America and Europe. With strong fundamentals we are looking forward to investing in new areas along with growth.

Share this post via:

Comments

There are no comments yet.

You must register or log in to view/post comments.