Visit with Agnisys at DAC 2023 in San Francisco July 10-12

I’d like to extend an invitation to you and your development team to visit with Agnisys in our booth, #2512, at this week’s Design Automation Conference (DAC) 2023, Monday, July 10-12.

In its 60^th year, DAC is recognized as the premier event for the design and design automation of electronic chips to systems, so you can count on team Agnisys to help you solve complex front-end design, verification, and validation problems. Our certified IDesignSpec™ Solution Suite leverages a golden executable specification to capture and centralize registers, sequences, and connectivity for Intellectual Property (IP) and System-on-a-Chip (SoC) projects.

Book time, in advance, with our solutions team to learn how our intuitive user interfaces and standards-based workflows dramatically reduce risk by eliminating development errors while significantly increasing productivity and efficiency through the automatic generation of collateral (output files) for the entire product development team.

And while at our booth, don’t forget to take our Quiz. Winners of this quiz (who score 8 or higher) will receive one of the following prizes: a portable charger, a portable JBL Clip 4 mini speaker, or a JBL Go 3 portable speaker. Everyone who scores 4 or higher is eligible for our end of day drawing for a Creality Resin 3D printer.

I hope you’ll also find time to join me on Tuesday, July 11^th, from 11:45AM to 1:00PM in room 3015, Moscone West, for an Accellera-sponsored luncheon and panel titled, “Tackling SoC Integration Challenges.”

With System-on-Chip (SoC) design becoming more and more widespread, the challenge of IP integration – IP created and verified with tools from different vendors – has been rapidly exacerbated. Accellera working groups are tackling these challenges by introducing new standardization initiatives such as the Security Annotation for Electronic Design Integration (SA-EDI) 1.0 Standard focused on helping IP providers identify security concerns, and the new Clock Domain Crossing (CDC) Working Group focused on creating a standard for CDC abstraction models to facilitate faster design IP integration. Agnisys has been an active and strong contributor to various Accellera working groups.

This lunch-time panel will focus on the efforts of the CDC Working Group to define a standard CDC collateral specification. The standard is aimed at easing SoC integration, enabling teams to integrate IPs verified using various CDC tools without sacrificing quality and design time. Panel members from the working group will share the key work in progress and look toward deliverables in the coming year. Attendees will have an opportunity to ask questions. If you’re interested in further details, please contact us or click on the image below to register.

If your development team needs to solve for the inevitable metastability in a
multi-clock-domain design, then you might enjoy the following article, . Agnisys provides a pushbutton solution for clock domain crossings related to register blocks that helps chip architects and engineers create an executable specification for the control and status registers (CSRs) and automatically generate outputs for software and hardware teams.

AGNISYS DEMOS AT DAC:

• IDesignSpec GDI: Capture addressable registers / IP spec in a robust variety of formats + functional behavior of the registers + the connectivity specification for the entire chip to reduce development time by 50% / improve quality 1000X
• IDS-Batch CLI: Command line capabilities for system development
• IDS-Verify: Reduce your verification engineer’s workload (over 40%) by automatically generating UVM based verification environment and tests + generate assertions to automatically verify the HSI layer + create custom tests to test register related functionality
• IDS-Validate: Generate C/C++ tests automatically for the Hardware-Software Interface layer to ensure that your product reaches the market flawlessly
• IDS-Integrate: Construct an SoC from constituent blocks using a connectivity specification in Tcl / Python to help automate your IP-XACT based packaging flow
• IDS-IPGen: Specify state-machines, data-path, and combinatorial logic in addition to addressable registers to auto-generate the design RTL and the UVM verification environment + generate AI based tests to ensure faster / complete code-coverage and functional coverage

BY SPECIAL REQUEST – schedule time to discuss these topics by clicking here

• Batch processing of PSS files for generation of test files
• Specialized editor for simultaneous multiple team member editing of PSS / SystemRDL files (generate outputs from it all in the cloud)
• AI for automatic generation of tests for designs
• TLM based SystemC generation
• AMBA-5 for AXI, AHB and APB
• Efficient creation of a top-level SoC (IP-XACT 2022)

If you won’t be going to this year’s DAC, but would like to learn more about specification automation solutions from Agnisys, we hope you’ll join us for the first in a three-part series of upcoming August webinars:

• Aug. 3: An Introduction to Correct-by-Construction Golden Specification-based IP/SoC Development

Be sure to save the date for the next topics in our webinar series:

• Aug. 17: IP-XACT 2022 : What’s New
• Aug. 31: Avoiding Metastability – CDC for Hardware & Software Interface

If you have any questions about correct-by-construction golden specification-based design, please contact us today!

Also Read:

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