Webinar: Avoiding Metastability in Hardware Software Interface (HSI) using CDC Techniques

Webinar: Avoiding Metastability in Hardware Software Interface (HSI) using CDC Techniques
by Admin on 11-30-2023 at 1:33 pm

*Please use your work email so we know who the audience is*

Various IP blocks within an SoC are often required to work in different clock domains in order to satisfy the power constraints. Clock domain crossing (CDC) challenges faced by design engineers include:

– Speed and power requirements lead to designs with multiple… Read More


Accellera and Clock Domain Crossing at #60DAC

Accellera and Clock Domain Crossing at #60DAC
by Daniel Payne on 08-02-2023 at 10:00 am

Accellera, clock domain crossing, #60DAC

Accellera sponsored a luncheon panel discussion at #60DAC, so I registered and attended to learn more about one of the newest working groups for Clock Domain Crossing (CDC). An overview of Accellera was provided by Lu Dai, then the panel discussion was moderated by Paul McLellan of Cadence, with the following panel members:

  • Anupam
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WEBINAR: Driving Golden Specification-Based IP/SoC Development

WEBINAR: Driving Golden Specification-Based IP/SoC Development
by Daniel Nenni on 07-19-2023 at 10:00 am

Correct By ConstructionGoldenSpec BasedIP SoCDevelopment

The ever-increasing demands placed on Intellectual Property (IP) and System-on-Chip (SoC) development teams have resulted in an ever-increasing need for automation solutions that can boost productivity without contributing to further risk. Certainly, demands for automation have long been the drivers behind the growth… Read More


The Inconvenient Truth of Clock Domain Crossings

The Inconvenient Truth of Clock Domain Crossings
by Anupam Bakshi on 07-17-2023 at 6:00 am

Figure 3

Almost everything that we do in chip design and verification was invented to raise the abstraction above schematics and polygons. Register-transfer-level (RTL) design, functional simulation, logic synthesis, floorplanning, and more fall into this category. Even the notion of binary circuits is an abstraction. Underneath… Read More


Webinar: An Introduction to Correct-by-Construction Golden Specification-based IP/SoC Development

Webinar: An Introduction to Correct-by-Construction Golden Specification-based IP/SoC Development
by Admin on 07-10-2023 at 2:06 pm

*Company Email is Required for Registration*

This webinar explores front-end automation advances that encompass an innovative register information management system to capture hardware functionality and addressable register map in a single “executable” specification.

Appropriate Audience:

● Architects/RTL… Read More


Visit with Agnisys at DAC 2023 in San Francisco July 10-12

Visit with Agnisys at DAC 2023 in San Francisco July 10-12
by Anupam Bakshi on 07-06-2023 at 6:00 am

Accellera Lunch 2023

I’d like to extend an invitation to you and your development team to visit with Agnisys in our booth, #2512, at this week’s Design Automation Conference (DAC) 2023, Monday, July 10-12.

In its 60th year, DAC is recognized as the premier event for the design and design automation of electronic chips to systems, so you can count on team… Read More


Webinar: Centralized Register Design and Verification from a Golden Specification

Webinar: Centralized Register Design and Verification from a Golden Specification
by Admin on 08-15-2022 at 3:07 pm

Learn how to bring the ease of a document editor to your system architects and designers to create an executable specification using IDesignSpec™. This specification fully describes and documents your design and automatically generates all downstream views.

Aug 18, 2022 10:00 AM in Pacific Time (US and Canada)

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Can We Auto-Generate Complete RTL, SVA, UVM Testbench, C/C++ Driver Code, and Documentation for Entire IP Blocks?

Can We Auto-Generate Complete RTL, SVA, UVM Testbench, C/C++ Driver Code, and Documentation for Entire IP Blocks?
by Kalar Rajendiran on 07-11-2022 at 6:00 am

IDSNG1

Whether it is fully autonomous driving, or wrinkle-free fabric, or ambient energy harvesting for powering electronic devices, each industry is chasing after its respective ultimate goal. For the semiconductor design industry, its goal is the capability to generate complete chip or IP in executable format from a high-level… Read More


Podcast EP92: The Impact of a Specification-Driven Correct-by-Construction Approach on Design and Verification with Agnisys

Podcast EP92: The Impact of a Specification-Driven Correct-by-Construction Approach on Design and Verification with Agnisys
by Daniel Nenni on 07-01-2022 at 10:00 am

Dan is joined by Anupam Bakshi, founder and CEO of Agnisys. Anupam has more than two decades of experience implementing a wide range of products and services in the high tech industry. Prior to forming Agnisys, he held various management and technical lead roles at companies such as Avid Technology Inc., PictureTel, Blackstone,… Read More