Konica Minolta Talks About High-Level Synthesis using C++

Konica Minolta Talks About High-Level Synthesis using C++
by Daniel Payne on 07-11-2019 at 8:00 am

In the early days of chip design circa 1970’s the engineers would write logic equations, then manually reduce that logic using Karnaugh Maps. Next, we had the first generation of logic synthesis in the early 1980’s, which read in a gate-level netlist, performed logic reduction, then output a smaller gate-level netlist.… Read More


An AI Accelerator Ecosystem For High-Level Synthesis

An AI Accelerator Ecosystem For High-Level Synthesis
by Bernard Murphy on 07-01-2019 at 10:00 am

AI accelerators as engines for object or speech recognition (among many possibilities), are becoming increasingly popular for inference in mobile and power-constrained applications. Today much of this inferencing runs largely in software on CPUs or GPUs thanks to the sheer size of the smartphone market, but that will shift… Read More


The Implications of the Rise of AI/ML in the Cloud

The Implications of the Rise of AI/ML in the Cloud
by Randy Smith on 06-14-2019 at 10:00 am

Recently, Daniel Nenni blogged on the presentation Wally Rhines gave at #56th DAC. Daniel provided a great summary, but I want to dive into a portion of the presentation in more detail. I love Wally’s presentations, but sometimes you cannot absorb the wealth of information he provides when you initially see it. It’s… Read More


Update on SystemC for High-Level Synthesis

Update on SystemC for High-Level Synthesis
by Tom Dillinger on 03-26-2019 at 12:00 am

The scope of current system designs continues to present challenges to verification and implementation engineering teams. The algorithmic complexity of image/voice processing applications needs a high-level language description for efficient representation. The development and testing of embedded firmware routines… Read More


Mentor Showcases Digital Twin Demo

Mentor Showcases Digital Twin Demo
by Bernard Murphy on 03-06-2019 at 6:00 am

Mentor put on a very interesting tutorial at DVCon this year. Commonly DVCon tutorials center around a single tool; less commonly (in my recent experience) they will detail a solution flow but still within the confines of chip or chip + software design. It is rare indeed to see presentations on a full system design including realistic… Read More


Catapult Design Checker Finds Coding Errors Before High Level Synthesis

Catapult Design Checker Finds Coding Errors Before High Level Synthesis
by Camille Kokozaki on 11-26-2018 at 12:00 pm

In a recent whitepaper Gagandeep Singh, Director of Engineering at Mentor, a Siemens Business outlines a flow using Catapult Design Checker that helps in early detection of coding errors as many companies are turning to High-Level Synthesis (HLS) methodology. This requires that high -level C++ models are correct, that ambiguities… Read More


Computer Vision and High-Level Synthesis

Computer Vision and High-Level Synthesis
by Daniel Payne on 03-15-2018 at 12:00 pm

Computer vision as a research topic has been around since the 1960’s and we are enjoying the benefits of this work in modern-day products all around us as robots with computer vision are performing an increasing number of tasks, even our farmers are using computer vision systems to become more productive:

  • AgEagle® has a drone
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HLS Rising

HLS Rising
by Bernard Murphy on 12-26-2017 at 7:00 am

No-one could accuse Badru Agarwala, GM of the Mentor/Siemens Calypto Division, of being tentative about high-level synthesis. (HLS). Then again, he and a few others around the industry have been selling this story for quite a while, apparently to a small and not always attentive audience. But times seem to be changing. I’ve written… Read More


High-Level Design for Automotive Applications

High-Level Design for Automotive Applications
by Bernard Murphy on 11-16-2017 at 7:00 am

Automotive markets have added pressure on semiconductor/systems design through demand for ISO26262 compliance – this we all know. But they have also changed the mix of important design types. Once class of design that has become very significant in ADAS, and ultimately autonomous applications, is image signal processing (ISP).… Read More


High Level Synthesis Update

High Level Synthesis Update
by Tom Dillinger on 06-29-2016 at 7:00 am

High-level synthesis (HLS) involves the generation of an RTL hardware model from a C/C++/SystemC description. The C code is typically referred to as abehavioraloralgorithmicmodel. The C language constructs and semantics available to architects enable efficient and concise coding – the code itself is smaller, easier to write/read,… Read More