New Tool that Synthesizes Python to RTL for AI Neural Network Code

New Tool that Synthesizes Python to RTL for AI Neural Network Code
by Daniel Payne on 05-21-2024 at 10:00 am

Catapult AI NN tool flow – Python to RTL

AI and ML techniques are popular topics, yet there are considerable challenges to those that want to design and build an AI accelerator for inferencing, as you need a team that understands how to model a neural network in a language like Python, turn that model into RTL, then verify that your RTL matches Python. Researchers from CERN,… Read More


HLS Design and Verification Seminar 2023 

HLS Design and Verification Seminar 2023 
by Admin on 11-07-2023 at 4:23 pm

We will be holding a high-level synthesis technical forum. The past few years have been held online, but this year we were able to return to the venue. We have prepared a variety of proposals, including success stories and new technology updates related to high-level design and verification, so please come and join us, even if

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Webinar: Stratus HLS Automated Power Shutoff to Minimize Power and Retention Registers

Webinar: Stratus HLS Automated Power Shutoff to Minimize Power and Retention Registers
by Admin on 08-21-2023 at 1:32 pm

Date: Wednesday, September 27, 2023

Time: 12:00pm PDT | 3:00pm EDT

Power Shutoff is a popular technique for saving power during functionally idle periods. Implementing Power Shutoff requires a detailed understanding of which resisters must be retained to enable bring-up from the power-off state. Identifying the minimal set… Read More


Webinar: An AI/ML Driven High-Level Synthesis Solution

Webinar: An AI/ML Driven High-Level Synthesis Solution
by Admin on 06-20-2023 at 4:16 pm

High-Level Synthesis (HLS) tools yield better PPA when the “right set” of optimization constraints and tool settings are applied. Determining the right set of constraints and settings requires design and tool experience and exploration. AI/ML technology has proven highly effective at exploring the solution… Read More


DUTh: Architectural Improvements for Low-Power and Functional Safety of Dataflow CNN Accelerators using HLS

DUTh: Architectural Improvements for Low-Power and Functional Safety of Dataflow CNN Accelerators using HLS
by Admin on 01-25-2023 at 2:36 pm

Deep Convolution Neural Networks (CNNs) are dominant in modern Machine Learning (ML) applications. Their acceleration directly in hardware calls for a multifaceted approach that combines high-performance, energy efficiency, and functional safety. These requirements hold for every CNN architecture, including both systolic

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A Fresh Look at HLS Value

A Fresh Look at HLS Value
by Bernard Murphy on 06-21-2022 at 6:00 am

Streaming min

I’ve written several articles on High-Level Synthesis (HLS), designing in C, C++ or SystemC, then synthesizing to RTL. There is unquestionable appeal to the concept. A higher level of abstraction enables a function to be described in less lines of code (LOC). Which immediately offers higher productivity and implies less bugs… Read More


HLS in a Stanford Edge ML Accelerator Design

HLS in a Stanford Edge ML Accelerator Design
by Bernard Murphy on 06-16-2022 at 6:00 am

AI for stanford min

I wrote recently about Siemens EDA’s philosophy on designing quality in from the outset, rather than trying to verify it in. The first step is moving up the level of abstraction for design. They mentioned the advantages of HLS in this respect and I refined that to “for DSP-centric applications”. A Stanford group recently presented… Read More


Smoother MATLAB to HLS Flow

Smoother MATLAB to HLS Flow
by Bernard Murphy on 12-09-2020 at 6:00 am

A better design path from MATLAB 1 min

It hard to imagine design of a complex signal processing or computer vision application starting somewhere other than in MATLAB. Prove out the algorithm in MATLAB, then re-model in Simulink, to move closer to hardware. First probably an architectural model, using MATLAB library functions to prove out behavior of the larger system.… Read More


#57DAC – Panel Discussion of High Level Synthesis

#57DAC – Panel Discussion of High Level Synthesis
by Daniel Payne on 07-28-2020 at 10:00 am

sean dart, Cadence

Presenters took a trip down memory lane at DAC this year by having a panel discussion on HLS (High Level Synthesis) spanning from 1974 to 2020, and that time period aligns with when I first graduated from the University of Minnesota in 1978, starting chip design at Intel, then later transitioning into EDA companies by 1986. MarilynRead More


What a Difference an Architecture Makes: Optimizing AI for IoT

What a Difference an Architecture Makes: Optimizing AI for IoT
by Bernard Murphy on 05-28-2020 at 6:00 am

HLS PPA results

Last week Mentor hosted a virtual event on designing an AI accelerator with HLS, integrating it together with an Arm Corstone SSE-200 platform and characterizing/optimizing for performance and power. Though in some ways a recap of earlier presentations, there were some added insights in this session, particularly in characterizing… Read More