I’ve written several articles on High-Level Synthesis (HLS), designing in C, C++ or SystemC, then synthesizing to RTL. There is unquestionable appeal to the concept. A higher level of abstraction enables a function to be described in less lines of code (LOC). Which immediately offers higher productivity and implies less bugs… Read More
Tag: hls
Webinar: Stratus HLS Automated Power Shutoff to Minimize Power and Retention Registers
Date: Wednesday, September 27, 2023
Time: 12:00pm PDT | 3:00pm EDT
Power Shutoff is a popular technique for saving power during functionally idle periods. Implementing Power Shutoff requires a detailed understanding of which resisters must be retained to enable bring-up from the power-off state. Identifying the minimal set… Read More
Webinar: An AI/ML Driven High-Level Synthesis Solution
High-Level Synthesis (HLS) tools yield better PPA when the “right set” of optimization constraints and tool settings are applied. Determining the right set of constraints and settings requires design and tool experience and exploration. AI/ML technology has proven highly effective at exploring the solution… Read More
DUTh: Architectural Improvements for Low-Power and Functional Safety of Dataflow CNN Accelerators using HLS
A Fresh Look at HLS Value
HLS in a Stanford Edge ML Accelerator Design
I wrote recently about Siemens EDA’s philosophy on designing quality in from the outset, rather than trying to verify it in. The first step is moving up the level of abstraction for design. They mentioned the advantages of HLS in this respect and I refined that to “for DSP-centric applications”. A Stanford group recently presented… Read More
Smoother MATLAB to HLS Flow
It hard to imagine design of a complex signal processing or computer vision application starting somewhere other than in MATLAB. Prove out the algorithm in MATLAB, then re-model in Simulink, to move closer to hardware. First probably an architectural model, using MATLAB library functions to prove out behavior of the larger system.… Read More
#57DAC – Panel Discussion of High Level Synthesis
Presenters took a trip down memory lane at DAC this year by having a panel discussion on HLS (High Level Synthesis) spanning from 1974 to 2020, and that time period aligns with when I first graduated from the University of Minnesota in 1978, starting chip design at Intel, then later transitioning into EDA companies by 1986. Marilyn… Read More
What a Difference an Architecture Makes: Optimizing AI for IoT
Last week Mentor hosted a virtual event on designing an AI accelerator with HLS, integrating it together with an Arm Corstone SSE-200 platform and characterizing/optimizing for performance and power. Though in some ways a recap of earlier presentations, there were some added insights in this session, particularly in characterizing… Read More
High-Level Synthesis and Open Source Software Algorithms
The DVCon conference and exhibition finished up in California just as the impact of the COVID-19 pandemic was ramping up in March, but at least they finished the conference by altering the schedule a bit. Umesh Sisodia, CEO at CircuitSutra Technologies presented at DVCON on the topic, Using High-Level Synthesis to Migrate Open… Read More