Webinar: From HLS Component to a Working Design

Webinar: From HLS Component to a Working Design
by Daniel Payne on 10-15-2019 at 10:00 am

Overview

Complex algorithms do not exist in a vacuum. After HLS is used to create an RTL component, to be useful, it needs to be integrated into a larger system. This means connecting it to other components, a processor, and even software. Once integrated, the system needs to be verified. The verification of the complete environment… Read More


Webinar: Implementing Machine Learning Hardware Using High-Level Synthesis

Webinar: Implementing Machine Learning Hardware Using High-Level Synthesis
by Daniel Payne on 10-08-2019 at 10:00 am

Overview

Neural networks are typically developed and trained in a high-performance 32-bit floating-point compute environment. But, in many cases a custom hardware solution is needed for the inference engine to meet power and real-time requirements. Each neural network and end-application may have different performance… Read More


Webinar: Using High-Level Synthesis to Accelerate Computer/Machine Vision Applications

Webinar: Using High-Level Synthesis to Accelerate Computer/Machine Vision Applications
by Daniel Payne on 10-01-2019 at 10:00 am

Overview

HLS has been used in multiple companies, projects, and designs targeting vision processing for the past several years. HLS adoption continues to grow because it is the fastest way to turn complex algorithms into efficient hardware implementations. HLS creates a methodology that enables design teams to rapidly react… Read More


AI Hardware Summit, Report #2: Lowering Power at the Edge with HLS

AI Hardware Summit, Report #2: Lowering Power at the Edge with HLS
by Randy Smith on 09-30-2019 at 10:00 am

I previously wrote a blog about a session from Day 1 of the AI Hardware Summit at the Computer History Museum in Mountain View, CA, held just last week. From Day 2, I want to delve into this presentation by Bryan Bowyer, Director of Engineering, Digital Design & Implementation Solutions Division at Mentor, a Siemens Business.… Read More


Webinar: HLS — What, How and Why Now?

Webinar: HLS — What, How and Why Now?
by Daniel Payne on 09-24-2019 at 10:00 am

Overview

HLS has been around for years, so why are we seeing such growth now? This webinar starts with an introduction of basic HLS concepts, design methodologies, best fits for HLS with customer use cases/highlights that explain the benefits they experienced and their adoption path. It will then move to a discussion of trends … Read More


Konica Minolta Talks About High-Level Synthesis using C++

Konica Minolta Talks About High-Level Synthesis using C++
by Daniel Payne on 07-11-2019 at 8:00 am

In the early days of chip design circa 1970’s the engineers would write logic equations, then manually reduce that logic using Karnaugh Maps. Next, we had the first generation of logic synthesis in the early 1980’s, which read in a gate-level netlist, performed logic reduction, then output a smaller gate-level netlist.… Read More


An AI Accelerator Ecosystem For High-Level Synthesis

An AI Accelerator Ecosystem For High-Level Synthesis
by Bernard Murphy on 07-01-2019 at 10:00 am

AI accelerators as engines for object or speech recognition (among many possibilities), are becoming increasingly popular for inference in mobile and power-constrained applications. Today much of this inferencing runs largely in software on CPUs or GPUs thanks to the sheer size of the smartphone market, but that will shift… Read More


The Implications of the Rise of AI/ML in the Cloud

The Implications of the Rise of AI/ML in the Cloud
by Randy Smith on 06-14-2019 at 10:00 am

Recently, Daniel Nenni blogged on the presentation Wally Rhines gave at #56th DAC. Daniel provided a great summary, but I want to dive into a portion of the presentation in more detail. I love Wally’s presentations, but sometimes you cannot absorb the wealth of information he provides when you initially see it. It’s… Read More


Update on SystemC for High-Level Synthesis

Update on SystemC for High-Level Synthesis
by Tom Dillinger on 03-26-2019 at 12:00 am

The scope of current system designs continues to present challenges to verification and implementation engineering teams. The algorithmic complexity of image/voice processing applications needs a high-level language description for efficient representation. The development and testing of embedded firmware routines… Read More


Mentor Showcases Digital Twin Demo

Mentor Showcases Digital Twin Demo
by Bernard Murphy on 03-06-2019 at 6:00 am

Mentor put on a very interesting tutorial at DVCon this year. Commonly DVCon tutorials center around a single tool; less commonly (in my recent experience) they will detail a solution flow but still within the confines of chip or chip + software design. It is rare indeed to see presentations on a full system design including realistic… Read More