Boost Verification Productivity with PSS 2.0 and Perspec

Boost Verification Productivity with PSS 2.0 and Perspec
by Admin on 06-10-2021 at 12:00 am

June 10, 2021

Overview

SoC level verification and validation is often the bottleneck of chip design projects due to lack of methodology and automation for creating system level stimulus and limited content reuse. Complex system use-cases, involve interactions between different elements in the system, are hard to write, model

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Happy Birthday UVM! A Very Grown-Up 10-Year-Old

Happy Birthday UVM! A Very Grown-Up 10-Year-Old
by Bernard Murphy on 02-16-2021 at 6:00 am

UVM logo min

.The UVM standard was first released by Accellera 10 years ago this month and is now by far the leading methodology for functionally verifying logic designs, especially at the block level. As I write, DVCon fast approaches so I talked to Tom Fitzpatrick, Verification Technologist at Siemens EDA (Mentor Graphics) for a perspective.… Read More


PSS, Test Realization and Reuse

PSS, Test Realization and Reuse
by Bernard Murphy on 03-31-2020 at 6:00 am

Generating tests from PSS

Mentor just released a white paper on this topic which I confess has taxed my abilities to blog the topic. It’s not that the white paper is not worthy – I’m sure it is. I’m less sure that I’m worthy to blog on such a detailed technical paper. But I’m always up for a challenge, so let’s see what I can make of this, extracting a quick and not very… Read More


Verification, RISC-V and Extensibility

Verification, RISC-V and Extensibility
by Bernard Murphy on 02-05-2020 at 6:00 am

RISC-V

RISC-V is obviously making progress. Independent of licensee signups and new technical offerings, the simple fact that Arm is responding – in fundamental changes to their licensing model and in allowing custom user extensions to the instruction set – is proof enough that they see a real competitive threat from RISC-V.

Which all… Read More


DVCon Is a Must Attend Event for Design and Verification Engineers

DVCon Is a Must Attend Event for Design and Verification Engineers
by Daniel Payne on 02-03-2020 at 10:00 am

dvcon 2020

Learning is a never-ending process for design and verification engineers, so outside of reading SemiWiki you likely want to attend at least a few events per year to keep updated, learn something new, attend a workshop, or even present something that has made your IC project work much better than before. Sure, DAC is always a great… Read More


Build More and Better Tests Faster

Build More and Better Tests Faster
by Bernard Murphy on 08-27-2019 at 5:00 am

Breker has been in the system test synthesis game for 12 years, starting long before there was a PSS standard. Which means they probably have this figured out better than most, quite simply because they’ve seen it all and done it all. Breker is heavily involved in and aligned with the standard of course but it shouldn’t be surprising… Read More


Easing Your Way into Portable Stimulus

Easing Your Way into Portable Stimulus
by Bernard Murphy on 09-13-2018 at 7:00 am

The Portable Stimulus Standard (PSS) was officially released at DAC this year. While it will no doubt continue to evolve, for those who were waiting on the sidelines, it is officially safe to start testing the water. In fact it’s probably been pretty safe for a while; vendors have had solutions out for some time and each is happy to … Read More


Don’t Stand Between The Anonymous Bug and Tape-Out (Part 2 of 2)

Don’t Stand Between The Anonymous Bug and Tape-Out (Part 2 of 2)
by Alex Tan on 03-16-2018 at 7:00 am


The second panel is about system coverage and big data. Coverage metrics have been used to gauge the quality of verification efforts during development. At system level, there are still no standardized metrics to measure full coverage. The emergence of PSS, better formal verification, enhanced emulation and prototyping techniques… Read More


An Advanced-User View of Applied Formal

An Advanced-User View of Applied Formal
by Bernard Murphy on 03-08-2018 at 7:00 am

Thanks to my growing involvement in formal (at least in writing about it), I was happy to accept an invite to this year’s Oski DVCon dinner / Formal Leadership Summit. In addition to Oski folks and Brian Bailey (an esteemed colleague at another blog site, to steal a Frank Schirrmeister line), a lively group of formal users attended… Read More


A Brief History of PSS at Breker

A Brief History of PSS at Breker
by Daniel Payne on 11-14-2017 at 12:00 pm

Verification engineers are hearing a lot about the Portable Stimulus Standard (PSS), and for good reason because it could potentially save them time and effort in doing their jobs much better. In order to get the big picture on what PSS is all about I contacted Adnan Hamid, founder and CEO of Breker Verification Systems, because … Read More