Having worked at several semiconductor intellectual property (SIP) companies, I know how important it is to have a strong design data management platform for tracking the development and distribution of SIP products. Everyone doing semiconductor design should care about design data management. But for an IP company, it is imperative. Life gets complex quickly when you start giving your customers different versions of the same IP. So, it got my attention when Vidatronic, a provider of energy-efficient analog and power management unit (PMU) IP, said they were willing to talk about their use of ClioSoft’s SOS Design Platform to develop their IPs.
First, a bit about Vidatronic. They have been around since 2010 and have a couple of interesting outside board members amongst some of the biggest names in semiconductors, including Hector Ruiz, Ph.D. (former CEO of AMD) and Mike Bartlett, M.S.E.E. (former Texas Instruments VP). Recently, Vidatronic announced that they will provide PMU and analog IP cores to ARM for use in their solutions and have also teamed up with Samsung Foundry to provide analog IP core designs for licensing through SAFE™, Samsung Advanced Foundry Ecosystem. They sport two primary engineering locations, one in Austin, Texas and one in Egypt. Their analog SoC IP portfolio includes power-management solutions including LDO linear voltage regulators, DC-DC switching converters, bandgap voltage references, and other support circuitry. They also provide radio-frequency solutions, including CMOS transmitters.
Based on this basic description of Vidatronic, we can see that they need to support many SIPs across a large number of design process nodes, where they also need to develop customized versions for certain customer/process node combinations. But when diving in deeper with Vidatronic, we find even stronger reasons to deploy ClioSoft’s SOS Design Platform:
- Reduced complexity and efficiency while supporting multiple sites
- Used in Texas and Egypt
- Supports real-time sharing of design data between the sites
- Performance needs for auto-synchronization and secure, efficient data transfer
- Easy to control/restrict design access
- Optimized disk usage using SOS smart caching (with links to cache work areas to optimize network storage)
- Read-only local copy work areas with exclusive or concurrent locking
- Support for Cadence Virtuoso platform
- Ability to manage complex hierarchical cell views
- Integrates well with Cadence Virtuoso
- Critical features for tracking multiple versions of each IP
- Easy to take and label design snapshots of the designs which helps in efficient collaboration between the teams
- “Revert back” feature for recovering to a stable version of the design data, if necessary
- Design teams can record important milestones, plus review and track open issues
- Use “visual design diff” to identify differences between two revisions of the schematic or layout of an IP
That is a lot of strong reasons for Vidatronic to utilize ClioSoft’s SOS Design Platform.
When I asked Moises Robinson, President and Co-Founder of Vidatronic about his company’s experience with ClioSoft, he told me “We selected ClioSoft’s SOS Design and IP Management Platform for our design needs about four years ago and we have been extremely happy with it ever since. The number one reason we chose ClioSoft was for its design collaboration features. Operating on a global scale is not without its challenges, but ClioSoft allows our engineers across the world to work seamlessly together on the same projects while maintaining tight control over revision histories so we never lose any of our work. Effective management of the different versions of our IP and efficient collaboration among our designers is integral to our success, and ClioSoft plays an important role in us ultimately delivering the highest quality IP to our customers.”
That is an impressive endorsement. Indeed, ClioSoft’s SOS Design Platform seems like a perfect tool for companies developing IPs over multiple sites worldwide.