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WEBINAR REPLAY: ClioSoft Facilitates Design Reuse with Cadence® Virtuoso®

WEBINAR REPLAY: ClioSoft Facilitates Design Reuse with Cadence® Virtuoso®
by Daniel Nenni on 10-23-2019 at 10:00 am
Categories: ClioSoft, EDA, Events

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In September, ClioSoft gave a SemiWiki webinar titled, Reusing Your IPs & PDKs Successfully With Cadence® Virtuoso®. I was happy to be the moderator of this webinar, having had the chance to work with ClioSoft’s team over many years. The webinar was informative while also being very time efficient. I think it … Read More

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WEBINAR: Reusing Your IPs & PDKs Successfully With Cadence® Virtuoso®

WEBINAR: Reusing Your IPs & PDKs Successfully With Cadence® Virtuoso®
by Randy Smith on 09-13-2019 at 10:00 am
Categories: ClioSoft, EDA, Events

I recently wrote about a ClioSoft® study with Google on using cloud platforms for EDA design and the importance of using persistent storage when doing that. ClioSoft will again be sharing important information on design productivity in the upcoming webinar, Reusing Your IPs & PDKs Successfully With Cadence® Virtuoso®. … Read More

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IP-XACT The Answer for IP Reuse

IP-XACT The Answer for IP Reuse
by Tom Simon on 04-09-2019 at 7:00 am
Categories: EDA, Magillem
3 Comments

To a lawyer, the term intellectual property means just about anything intangible that has value. However, when you bring that term up in the context of semiconductor design, it means something pretty specific to most people. Yet the implied meaning of the term intellectual property (IP) within the semiconductor field has changed… Read More

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Hierarchy Applied to Semiconductor IP Reuse

Hierarchy Applied to Semiconductor IP Reuse
by Daniel Payne on 11-30-2017 at 12:00 pm
Categories: EDA, Methodics

When I first started doing IC design back in 1978 we had hierarchical designs, and that was doing a relatively simple 16Kb DRAM chip with only 32,000 transistors using 6um (aka 6,000 nm) design rules. SoC designs today make massive use of hierarchy at all levels of IC design: IC Layout, transistor netlist, gate level netlist, RTL … Read More

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Scaling Enterprise Potential with ClioSoft’s designHUB platform

Scaling Enterprise Potential with ClioSoft’s designHUB platform
by Mitch Heins on 05-02-2017 at 10:00 am
Categories: ClioSoft, EDA

Image RemovedI’ve had the privilege over the years to be a part of a lot of great companies, teams and projects. Some of these efforts were quite successful while others were not. It begs the question of why is it so hard to enable design reuse and capture the untapped potential of the collective intelligence within our companies? … Read More

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Dassault Systemes Hosts New Microsite Focused on IP Reuse Challenges

Dassault Systemes Hosts New Microsite Focused on IP Reuse Challenges
by Mitch Heins on 01-04-2017 at 12:00 pm
Categories: Dassault Systemes, IP

Image RemovedI recently wrote an article about networks-on-chip (NoC) and how Systems-On-Chip integrated circuits (SoCs) are becoming increasingly more complex and heterogeneous in nature. While researching for that article I came upon a new micro-site by Dassault Systemes that goes into great detail about the operational… Read More

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Behind the 3DEXPERIENCE for silicon

Behind the 3DEXPERIENCE for silicon
by Don Dingee on 10-31-2016 at 4:00 pm
Categories: Dassault Systemes, EDA

We’ve been covering the Dassault Systèmes “Silicon Thinking” platform for a while here, but, as I’m often prone to do, I wanted to explore the backstory to uncover more about the concept. With over 25M users of their product lifecycle management (PLM) solutions, why is Dassault Systèmes becoming so interested in semiconductor… Read More

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10 challenges in IP design collaboration

10 challenges in IP design collaboration
by Don Dingee on 07-18-2016 at 4:00 pm
Categories: ClioSoft, EDA

Enterprise design management can be summed up in one word: collaboration. Intellectual property (IP) reuse and the success of distributed system-on-chip (SoC) design efforts depend strongly on how well designers can collaborate. As time-to-market windows have shortened, the challenges around design collaboration have… Read More

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Managing and reusing IP in a build-borrow-buy era

Managing and reusing IP in a build-borrow-buy era
by Don Dingee on 04-01-2016 at 4:00 pm
Categories: ClioSoft, EDA

Make-versus-buy inadequately describes what we do now in electronic systems design. We are on a continuum of design IP acquisition and use decisions, often with a portfolio of active projects and future projects depending on the outcome. Properly managing IP means adopting a build-borrow-buy mindset and tools capable of handling… Read More

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The Case for Data Management Amid the Rise of IP in SoCs

The Case for Data Management Amid the Rise of IP in SoCs
by Majeed Ahmad on 09-02-2015 at 12:00 pm
Categories: ClioSoft, EDA

In the late 1990s and early 2000s, during the adolescent days of the system-on-chip (SoC) design movement, there was a lot talk about IP and design reuse, but it was seldom put into practice. A decade later, SoC turned into a juggernaut with a tripartite alliance of chipmakers, IP suppliers and semiconductor manufacturing fabs.… Read More