Once again with Synopsys and Arteris, the innovation is coming to solve an issue, faced by their potential customers: “In our research, we’ve found that almost half of project delays are caused by problems with the system architecture design and specification,” said Chris Rommel, vice president, embedded software and hardware, VDC Research. “Many of these architecture problems are related to escalating SoC complexity, including multicore requirements. Therefore, solutions like the one developed by Synopsys and Arteris to efficiently analyze multicore SoC architectures early in the design flow should become increasingly valuable as engineering teams look for ways to help improve project schedules and performance results.”
From a pure business point of view, Arteris and Synopsys teaming up to solve problems related to SoC complexity, including (ARM based ?) multicore requirements makes a lot of sense: both ARM and Synopsys have invested into Arteris, along with Qualcomm, the others being VC. When building a partnership, this is a very good sign of success when the two companies also have common business goals! And that’s good for the future customers, as they know that they will invest money, and also large engineering resources, into a solution which has a real future – which is not only a good way to make market communication! You can see the PR here.
Let’s have a look at what is behind this communication. The SoC development platform from Synopsys, Platform Architect environment with Multicore Optimization Technology (MCO), has been enhanced with transactors and analysis monitor support for Arteris’ FlexNoC interconnect models. The new MCO offers system architects three distinct advantages for early performance analysis and optimization of complex designs:
1.obtaining fully-instrumented performance models before software and RTL availability,
2.clearly measuring and visualizing the dynamic behavior and performance bottlenecks of multicore designs, and
3.automating the design flow to enable developers to explore hundreds of architecture alternatives in days versus weeks or months with paper specifications and RTL methods
The benefit of this faster turnaround time is that architects using FlexNoC interconnect IP can more fully explore and optimize their multicore architectures and then avoid to over- or under-design their SoC. Both can have a dramatic cost impact: if you over-design the SoC, you will spend endless time to complete the design and release it to production, loosing precious Time-To-Market, which can easily turn into much more money than the already large SoC development cost. If you under-design the SoC, you will probably hit the market window, but with a product comparing poorly with the competition, then lose market share.
“Our goal is to help system designers and architects avoid late discovery of system performance problems that can be extremely costly for both project schedules and budgets,” said John Koeter, vice president of marketing for IP and systems at Synopsys. “By starting architecture analysis and optimization at the transaction-level with Arteris’ FlexNoC interconnect models in Synopsys’ Platform Architect MCO, we offer SoC architects the ability to perform accurate simulation of the multicore system and its most critical application use-cases earlier. With this combination they can achieve the best balance of performance, power and cost at a time in the development process where they have the greatest impact.”
“Arteris FlexNoC’s integration with Synopsys’ Platform Architect MCO environment allows our customers to create better SoCs in less time,” said K. Charles Janac, president and CEO of Arteris. “Integration of the two technologies allows SoC designers to have the same quick turn-around simulation times they experience today with FlexNoC, while gaining critical benefits from the more realistic simulation and earlier analysis of their application scenarios.”
I have blogged in previous post about Arteris FlexNoC’s silicon-proven commercial network-on-chip interconnect IP offering the ability to reduce the number of interconnect wires and logic required for multicore SoC design. Reducing the interconnect wires and logic gates resolves routing congestion and timing closure issues at the back-end place-and-route stage, resulting in shorter development cycle time, faster SoC frequencies, smaller SoC area and less SoC power.
I have also blogged about Sonics vs Arterislegal battle(s), but I honestly prefer to discuss about such a partnership, as it clearly demonstrate who is bringing real innovation on this IP market!
Arteris and Synopsys’ integration is available today for users of Arteris FlexNoC version 2.6 or later, and Synopsys’ Platform Architect MCO tool version G-2011.06-SP2 or later. For more information on Arteris’ FlexNoC interconnect IP, please visit: www.arteris.com/flexnoc. For information on Synopsys’ Platform Architect MCO tool environment, please visit: http://www.synopsys.com/platformarchitect.