Webinar: Gate-Level Simulations at Warp Speed with the Xcelium Multi-Core App

Webinar: Gate-Level Simulations at Warp Speed with the Xcelium Multi-Core App
by Admin on 10-25-2023 at 2:50 pm

Are you ready to lead the way in gate-level digital simulations (GLS)? Dive into Cadence’s exclusive webinar and uncover the revolutionary Xcelium Multi-Core (MC) App—a game changer for GLS, allowing you to parallelize and expedite simulations like never before.

What You’ll Gain:

Insight: Understand why the Xcelium… Read More


MPSOC

MPSOC
by Admin on 02-20-2020 at 10:46 am

As you all know, the World Health Organization has declared COVID-19 (Coronavirus) to be a pandemic. Many governments have enacted travel bans, and numerous countries and local governments are prohibiting large or even moderately-sized public gatherings. Such bans on travel and public gatherings are likely to increase in

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New ARC VPX DSP IP provides parallel processing punch

New ARC VPX DSP IP provides parallel processing punch
by Tom Simon on 10-29-2019 at 6:00 am

The transition to the digital age from a mostly analog world really began with the invention of the A-to-D and D-to-A converters. However scalar processors can easily be overwhelmed by the copious data produced by something as simple as an audio stream. To solve this problem and to really jumpstart the digital age, the development… Read More


ARMing AI/ML

ARMing AI/ML
by Bernard Murphy on 03-24-2017 at 7:00 am

There is huge momentum building behind AI, machine learning (ML) and deep learning; unsurprisingly ARM has been busy preparing their own contribution to this space. They announced this week a new multi-core micro-architecture called DynamIQ, covering all Cortex-A processors, whose purpose is in their words, “to redefine Read More


It’s a heterogeneous world and cache rules it now

It’s a heterogeneous world and cache rules it now
by Don Dingee on 09-28-2016 at 4:00 pm

Cache evolved when the world was all about homogeneous processing and slow and expensive shared memory. Now, compute is just part of the problem – devices need to handle display, connectivity, storage, and other tasks, all at the same time. Different, heterogeneous cores handle different workflows in the modern SoC, and the burden… Read More


Getting Maximum Performance Bang for Your Buck through Parallelism

Getting Maximum Performance Bang for Your Buck through Parallelism
by Bernard Murphy on 06-26-2016 at 12:00 pm

Finding a way to optimally parallelize linear code for multi-processor platforms has been a holy grail of computer science for many years. The challenge is that we think linearly and design algorithms in the same way, but then want to speed up our analysis by adding parallelism to the algorithms we have already designed.

But the … Read More


Tracing Insight into Advanced Multicore Systems

Tracing Insight into Advanced Multicore Systems
by Pawan Fangaria on 01-22-2015 at 7:00 am

After knowing about the challenges involved in validating multicore systems and domains of system and application level tracing as explained by Don Dingee in his article “Tracing methods to multicore gladness” which is based on the first part of Mentor Embedded multicore whitepaper series, it’s time to take a deeper insight … Read More


Tracing methods to multicore gladness

Tracing methods to multicore gladness
by Don Dingee on 01-18-2015 at 9:00 am

Multiple processor cores are now a given in SoCs. Grabbing IP blocks and laying them in a multicore design may be the easy part. While verification is extremely important, it is only the start – obtaining real-world performance depends on the combination of multicore hardware and actual application software. What should engineers… Read More


SoCs should invest in a strong cache position

SoCs should invest in a strong cache position
by Don Dingee on 12-30-2014 at 4:00 pm

Like most technology firms, Apple has been home to many successes, and some spectacular defeats. One failure was Project Aquarius. At the dawn of the RISC era, before ARM architecture was “discovered” in Cupertino, engineers were hunkered over a Cray X-MP/48. The objective was to design Apple’s own quad core RISC processor to … Read More


I’d give my right ARM to be ambidextrous

I’d give my right ARM to be ambidextrous
by Don Dingee on 05-09-2014 at 8:00 am

Baseball loves a good switch hitter – from Frisch to Mantle to Rose to Murray to Jones, they are a rare and valuable commodity. AMD is calling on ambidexterity for its processors in 2015 and beyond, this week tipping plans for 20nm “Project SkyBridge” parts in either ARM or X86 with a common footprint. What remains to be seen is where… Read More