WEBINAR REPLAY: ClioSoft Facilitates Design Reuse with Cadence® Virtuoso®

WEBINAR REPLAY: ClioSoft Facilitates Design Reuse with Cadence® Virtuoso®
by Daniel Nenni on 10-23-2019 at 10:00 am
Categories: ClioSoft, EDA, Events

In September, ClioSoft gave a SemiWiki webinar titled, Reusing Your IPs & PDKs Successfully With Cadence® Virtuoso®. I was happy to be the moderator of this webinar, having had the chance to work with ClioSoft’s team over many years. The webinar was informative while also being very time efficient. I think it is important for… Read More

July 29, 2019January 8, 2020

Virtuoso Adapts to Address Cyber Physical Systems

Virtuoso Adapts to Address Cyber Physical Systems
by Tom Simon on 07-29-2019 at 2:00 pm
Categories: Automotive, Cadence, EDA

LIDAR is a controversial topic, with even Elon Musk weighing in on whether it will ever be feasible for use in self driving cars. His contention is that the sensors will remain too expensive and potentially be unreliable because of their mechanical complexity. However, each of the sensors available for autonomous driving have … Read More

January 21, 2019January 8, 2020

At Last, Package and Chip integration for RF Design

At Last, Package and Chip integration for RF Design
by Tom Simon on 01-21-2019 at 7:00 am
Categories: Cadence, EDA

It seems that it has always been that there were packages and ICs, and in the design tool world “never the twain shall meet”. The tools for designing packages were completely separate from the tools used to design IC’s. This was so profoundly true that even after Cadence merged with Valid Logic back in the early 90’s, their Allegro … Read More

December 17, 2018January 10, 2020

Photonics with CurvyCore

Photonics with CurvyCore
by Alex Tan on 12-17-2018 at 12:00 pm
Categories: Cadence, EDA, Silicon Photonics

As a preferred carrier to data or energy, photonics technology is becoming broad and diverse. In IC design, silicon-photonics technology has been the enabler of new capabilities and has revolutionized many applications as Moore’s-based scaling started to experience a slowdown. It acts as new on-chip inductor in HPC design … Read More

October 30, 2018January 11, 2020

Solving and Simulating in the New Virtuoso RF Solution

Solving and Simulating in the New Virtuoso RF Solution
by Tom Simon on 10-30-2018 at 12:00 pm
Categories: Cadence, EDA

Cadence has done a good job of keeping up with the needs of analog RF designs. Of course, the term RF used to be reserved for a thin slice of designs that were used specifically in RF applications. Now, it covers things like SerDes for networking chips that have to operate in the gigahertz range. Add that to the trend of combining RF and… Read More

December 19, 2017

Is there anything in VLSI layout other than “pushing polygons”? (4)

Is there anything in VLSI layout other than “pushing polygons”? (4)
by Dan Clein on 12-19-2017 at 12:00 pm
Categories: EDA

The year is now 1991 and in search for a more peaceful life we decided to move to Canada. At that time, very few companies had advanced flows in VLSI but Ottawa having BNR, Northern Telecom, Mitel, etc., looked to be the most promising place. After a few hiccups in finding a job, I landed in MOSAID, a small company with35 people at that … Read More

March 30, 2017June 14, 2019

Cadence Expands Integrated Photonics Beachhead

Cadence Expands Integrated Photonics Beachhead
by Mitch Heins on 03-30-2017 at 4:00 pm
Categories: Cadence, EDA, Silicon Photonics

In November of 2016, I made a bold statement that October 20, 2016 would stand as a watershed day in integrated photonics. The reason for this claim was that GLOBALFOUNDRIES proclaimed that integrated photonics was real and here to stay. The same week I wrote an article about Cadence Design Systems securing a photonic beachhead … Read More

February 13, 2017June 14, 2019

Qorvo Uses ClioSoft to Bring Design Data Management to RF Design

Qorvo Uses ClioSoft to Bring Design Data Management to RF Design
by Mitch Heins on 02-13-2017 at 12:00 pm
Categories: ClioSoft, EDA

A couple weeks ago I gave a heads-up about a webinar that was being hosted by ClioSoft, Qorvo and Keysight. The topic of the webinar was how to manage custom RF designs across multiple design teams and CAD flows. The webinar was held on February 1[SUP]st[/SUP] and included presentations by Marcus Ray of Qorvo and Michele Azarian of… Read More

October 21, 2016June 14, 2019

Fabless Photonic Design Flow Takes Shape as Cadence teams up with Lumerical and PhoeniX

Fabless Photonic Design Flow Takes Shape as Cadence teams up with Lumerical and PhoeniX
by Mitch Heins on 10-21-2016 at 4:00 pm
Categories: Cadence, EDA, Silicon Photonics

This week Cadence Design, Lumerical Solutions and PhoeniX Software hosted a two-day photonic summit and workshop. The first day had nearly 100 registered participants and featured industry leaders from Global Foundries, UCSB, MIT, Hewlett Packard Enterprise, General Electric, Boeing, Rockley Photonics, and Juniper Networks… Read More

May 12, 2016June 14, 2019

Getting Low Power Design Right in Mixed Signal Designs

Getting Low Power Design Right in Mixed Signal Designs
by Bernard Murphy on 05-12-2016 at 4:00 pm
Categories: Cadence, EDA

Mixed-signal design creates all sorts of interesting problems for implementation and verification flows, particularly when it comes to design for low power. We tend to think of mixed-signal as a few blocks like PLLs, ADCs and PHYs on the periphery of the design. Constrain and verify the digital power requirements up to analog … Read More

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