As a preferred carrier to data or energy, photonics technology is becoming broad and diverse. In IC design, silicon-photonics technology has been the enabler of new capabilities and has revolutionized many applications as Moore’s-based scaling started to experience a slowdown. It acts as new on-chip inductor in HPC design and fast connectivity in network infrastructure.
At the Cadence Photonics Summit and Workshop 2018 held in San Jose last month, Cadence showcased its CurvyCore Infrastructure, a new technology intended for photonics applications. It is a native infrastructure in the Cadence Virtuoso custom IC design platform, allowing designers to create and edit complex curvilinear shapes common in photonics, RF, MEMs, microfluidics and conformal metal routing.
The State of Photonics Technology
The CurvyCore technology addresses markets and technologies that span from silicon photonics switches and interconnects for HPC/Datacenter, medical sensing applications, LiDAR, aerospace, MEMs to carbon nanotube conductors. According to Dr. Vladimir Stojanovic from UC Berkeley, who gave a keynote at the Cadence 2018 Photonic Summit, the current photonics integration with advanced electronics leverages CMOS transistor performance, its process fidelity and package integration, to enable emerging SoCs for various applications ranging from computing to sensing and imaging.
Based on his team’s research, the sweet spot for a “zero-change” silicon photonics platforms used in this monolithic integration technology is of either 45nm or 32nm SOI CMOS processes –they are suitable for adding photonic capability and enhancing integrated system applications such as main communication of computing tasks without involving complicated 3D integration efforts or double-patterning for EUV. Figure 1 captures the optical I/O landscape as well as the application of photonics on RISC-V microprocessor and DRAM.
Silicon photonics application for fast interconnects also evolved from a data center, off-chip centric type to be more integrated as on-chip feature in both microprocessor and PIM (Photonic-Interconnected DRAM) designs. The open-source RISC-V microprocessor with photonic on-chip interconnect was first implemented as single, electronics-optics hybrid chip, dual-core 1.65Ghz processor in CMOS 45nm SOI.
Challenges to Silicon Photonics
Embracing silicon photonics is an evolving process as handling curvilinear physical shapes is challenging. Unlike the traditional Manhattan polygons, custom design of curvilinear geometries is prone to misalignment, roundoff errors and manufacturing problems.
It is an effort intensive undertaking as its associated Pcell creation is cumbersome and time consuming. Additionally, a lack of common infrastructure leads to many ad-hoc, non-replicable and sub-optimal flows –translating to complex DRC/LVS problems to fix. All of these drives the need of having a robust platform to address the overall physical design automation.
CurvyCore Technology and Its Key Benefits
For an optimal performance, the CurvyCore technology has been natively implemented in the Virtuoso platform. The CurvyCore infrastructure has a three-tier data model and is an extension to the Virtuoso advanced-node platform, which sits on a high-performance symbolic mathematical engine.
As part of the Virtuoso expanded data-model, the CurvyCore infrastructure provides full access to all levels of design captures –from building block to actual symbolic expressions, enabling the creation and maintenance of differentiated curvy IP. For example, figure 3 shows phase shifters for a LiDAR (Light Detection And Ranging) application comprises of orthogonal polygons for the electrical connections and curvy geometries for optical interconnect –both of which can be concurrently viewed and manipulated.
The diagram in figure 4 illustrates the CurvyCore data model starting with the mathematical core which consists of an accurate mathematical representation thru symbolic equations, then is followed by the second layer (in magenta) that captures any curve geometries discretized to its equivalent shapes, and the top, physical layer (in pink), that contains the layout polygons in OA shapes. The combination of curvilinear discretization, boolean and sizing operations enables design rule fixing related to photonic complex shapes.
Aside from enabling the creation and editing of complex curvilinear shapes, the CurvyCore integration with the Cadence Virtuoso custom IC design platform leverages a unified design environment for the development of multi-fabric systems. It has new APIs to allow complex PCells creation and efficient data model to support high-performance editing or storage of curvilinear shapes within the Virtuoso design platform.
CurvyCore also supplements the Virtuoso Layout Suite and works seamlessly with the most advanced Virtuoso features, allowing true co-design and integration of electronics and curvilinear features. For example, during the Cadence Photonics workshop attendees were given the opportunity to use the Virtuoso custom IC design platform to view or edit a LiDAR photonics IC and to perform co-simulation of beam steering using Spectre® AMS Designer, MATLAB and Lumerical INTERCONNECT as part of a test-drive of the CurvyCore infrastructure implementation in the Virtuoso platform.
The CurvyCore technology is planned for general availability in Q1-2019.