It seems that it has always been that there were packages and ICs, and in the design tool world “never the twain shall meet”. The tools for designing packages were completely separate from the tools used to design IC’s. This was so profoundly true that even after Cadence merged with Valid Logic back in the early 90’s, their Allegro Board products were not integrated with the Cadence Virtuoso IC tools. It’s not that they did not try. Cadence CEO Joe Costello tried valiantly to coax the two solutions into a common front end. I was there and lived through the turmoil. Perhaps the time was not ripe, therefore satisfying the need could be delayed.
However, many changes have occurred in electronics design that have made the integration between package and chip design essential. Nowhere is this truer than in the RF design space. Not only are the chips running faster, but more complex interconnections between them in the package and on interposers requires coordinated design, verification and closure. Lastly, the addition of multi-technologies like GaAs, SiGe, GaN, etc. have driven RF designs to multiple substrates, necessitating multichip packaging.
One of the main challenges created in RF flows is the need for EM analysis, both for interconnect and for a wide range of passive device types. This requirement spans the hierarchy, and includes on-chip devices such as MOM and MIM caps, inductors, critical nets and transmission lines. Also, EM effects can be profound for package nets. Finally, due to close proximity in some cases it is necessary to look at EM coupling between package and on chip structures. Even though there are EM tools that can address each of these domains, they often are hard to set up and present problems when it comes to inserting the generated models back into the design flow while maintaining design consistency across multiple views.
Design teams are often working on each of the pieces of a design concurrently, which makes the exchange of design data and the ongoing modifications essential. I’m sure everyone reading this has a horror story of a multi-chip module encountering issues due to out of sync design data that comes from batch transfers of interface specifications.
Cadence finally came back to the issue of module, package and chip design integration and the results look like just what is needed. Cadence has the benefit of strong, but separate, design solutions for each of these. Now with their Cadence Virtuoso RF Solution they have created the links in Virtuoso schematic to capture the entire schematic, including package and module. With a single golden schematic for the entire design they eliminate one of the major problem spots in the flow.
Even more interesting is how they added package layers to the IC technology file. With one unified technology file there is no more need to kludge together ad hoc layers in Virtuoso to add packaging information. Cadence has even added primitives for arcs and all angle routing so that package geometries can be represented without translation errors or dead-end data movement.
With all the elements captured in an integrated system, teams can be certain that interface changes will propagate through the hierarchy and ensure that everything stays in sync.
Cadence may be creating a revolution in RF design. They have also done extensive integration with board, package and chip EM solvers to ensure that high frequency effects are modeled and easily included in simulations. There are so many parts to this consolidated flow that it is hard to summarize. I suggest looking at a white paper they have written that digs deeper into the many facets of this solution.
After having seen the tumult after the Cadence – Valid merger, I can say that it is satisfying to see the vision finally coming to fruition. These changes would seem to cement Cadence leadership in the RF design space.