Increase Efficiency and Reduce Risks with IC and Package Co-Design Flows

Increase Efficiency and Reduce Risks with IC and Package Co-Design Flows
by Admin on 06-16-2022 at 12:00 am

Date: Thursday, June 16, 2022

Time: 11:00am – 12:00pm (PDT)

Overview

System designers face increasing challenges in meeting technical specifications and time-to-market requirements. While process nodes continue to shrink, the complexity of packages continues to grow. Large pin counts of flipped and rotated ICs may… Read More


Increase Efficiency and Reduce Risks with IC and Package Co-Design Flows

Increase Efficiency and Reduce Risks with IC and Package Co-Design Flows
by Admin on 06-14-2022 at 12:00 am

Date: Tuesday, June 14, 2022

Time: 09:00 BST / 10:00 CEST / 11:00 EEST and Israel / 13:30 IST

System designers face increasing challenges to meet technical specification and time-to-market requirements. While process nodes continue to shrink, the complexity of packages continue to grow. Large pin counts of flipped and rotated

Read More

CadenceTECHTALK: Increase Efficiency and Reduce Risks with IC and Package Co-Design Flows – EMEAI

CadenceTECHTALK: Increase Efficiency and Reduce Risks with IC and Package Co-Design Flows – EMEAI
by Admin on 06-14-2022 at 12:00 am

EMEAI Session

Date: Tuesday, June 14, 2022

Time: 09:00 BST / 10:00 CEST / 11:00 EEST and Israel / 13:30 IST

System designers face increasing challenges to meet technical specification and time-to-market requirements. While process nodes continue to shrink, the complexity of packages continue to grow. Large pin counts of flipped

Read More

Maximizing ASIC Performance through Post-GDSII Backend Services

Maximizing ASIC Performance through Post-GDSII Backend Services
by Kalar Rajendiran on 03-04-2021 at 6:00 am

Panel 1 Alchip – HPC ASIC Manufacturing Done Your Way 1030x579 1

ASICs by definition are designed to meet the respective applications’ requirements. ASIC engineers deploy various design techniques to maximize performance, minimize power and reduce chip size. But is there more that can be done after the GDSII is taped out? A recent press release from Alchip Technology dated Feb 4, 2021 claims… Read More


Optimizing High Performance Packages calls for Multidisciplinary 3D Modeling

Optimizing High Performance Packages calls for Multidisciplinary 3D Modeling
by Tom Simon on 10-16-2019 at 10:00 am

For all the time we spend thinking and talking about silicon design, it’s easy to forget just how important package design is. Semiconductor packages have evolved over the years from very basic containers for ICs into very specialized and highly engineered elements of finished electronic systems. They play an important role … Read More


Solving the EM Solver Problem

Solving the EM Solver Problem
by Tom Simon on 04-03-2019 at 7:00 am

The need for full wave EM solvers has been creeping into digital design for some time. Higher operating frequencies – like those found in 112G links, lower noise margins – caused by multi level signaling such as in PAM-4, and increasing design complexity – as seen in RDL structures, interposers, advanced connector… Read More


At Last, Package and Chip integration for RF Design

At Last, Package and Chip integration for RF Design
by Tom Simon on 01-21-2019 at 7:00 am

It seems that it has always been that there were packages and ICs, and in the design tool world “never the twain shall meet”. The tools for designing packages were completely separate from the tools used to design IC’s. This was so profoundly true that even after Cadence merged with Valid Logic back in the early 90’s, their Allegro … Read More


Solving and Simulating in the New Virtuoso RF Solution

Solving and Simulating in the New Virtuoso RF Solution
by Tom Simon on 10-30-2018 at 12:00 pm

Cadence has done a good job of keeping up with the needs of analog RF designs. Of course, the term RF used to be reserved for a thin slice of designs that were used specifically in RF applications. Now, it covers things like SerDes for networking chips that have to operate in the gigahertz range. Add that to the trend of combining RF and… Read More


Power Noise Sign-off at #53DAC

Power Noise Sign-off at #53DAC
by Daniel Payne on 05-29-2016 at 7:00 am

When I hear the company name of ANSYS the first EDA tool category that comes to mind is power noise sign-off. Going to DAC is a great way to find out what’s new with EDA, IP and foundries. There are three places that you can find ANSYS at DAC this year:… Read More


Boost the Market for Interposer and 3D ICs with Assembly Design Kits

Boost the Market for Interposer and 3D ICs with Assembly Design Kits
by Beth Martin on 07-29-2015 at 6:00 pm

The traditional system-on-chip (SoC) design process has fully qualified verification methods embodied in the form of process design kits (PDKs). Why is it that chip design companies and assembly houses have no IC/package co-design sign-off verification process?

Package die are often produced using multiple processes and… Read More