When I hear the company name of ANSYS the first EDA tool category that comes to mind is power noise sign-off. Going to DAC is a great way to find out what’s new with EDA, IP and foundries. There are three places that you can find ANSYS at DAC this year:
- ANSYS booth #1449
- Samsung booth #607
- TSMC booth #1933
Chip and package designers have several pertinent issues that ANSYS experts can talk about:
Semiconductor customers are going to talk about four different design and reliability topics and how they used ANSYS tools to both simulate and optimize their designs. You do have to request participation for these four workshops that each run for two hours:
Industry Trends on Low Power RTL Design and Analysis
In-design Optimization for Accelerated Design Closure
Chip-Package-System Simulation for Power, Signal and Thermal
Reliability Challenges for Advanced SoC and IP Designs
Best Practices Seminars
There are seven seminar topics to choose from at the ANSYS booth and these are one hour time slots:
- Ensuring Silicon Success on Sub 16nm Ultra-Large SoCs
- Reliability Analysis for Next Generation Fan-Out Wafer-Level Packaging
- Ensuring ESD Robustness for IPs and SoCs
- Accurate On-die Modeling Needs for System Level PI, SI & Thermal Needs
- Optimizing Die-size Using In-design Analysis
- Power-Noise and Reliability for Analog & Mixed Signal IPs
- Six Steps to Lower Power RTL Design
Register for the seminars online here.
DAC Designer Track
There are some 25 sessions in the DAC Designer Track where ANSYS tools are discussed in poster sessions, reuse and reliability, power management and low power IP.
If you are in the automotive, IoT or Mobile industries then plan on learning more about reliability, magnetics, mechanical and thermal simulations are used in the booth theatre. These are open to all DAC attendees, so no registration is required.
ANSYS has a lot going on at DAC this year for chip and package engineers, and I hope to meet up with Vic Kulkarni, a Sr. VP & GM of the semiconductor business unit.
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