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DesignCon 2023by Admin on 11-30-2022 at 12:53 pm
The Must Attend Event for Chip, Board, and Systems Design Engineers
DesignCon is the premier high-speed communications and system design conference and exposition, offering industry-critical engineering education in the heart of electronics innovation — Silicon Valley.
Take Your Electronic Design Expertise to the Next
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Join us on Thursday, November 3rd to learn how Lawrence Berkeley National Laboratory, Fermilab, and Brookhaven National Laboratory collaborated and designed a custom ASIC chip to run at extremely cold temperatures, so that it can detect neutrinos!
Register Today!
Here’s what you can learn:
- Why study neutrinos and how to detect
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Paul Karazuba, VP of Marketing, Expedera & John Min, Director of Field Application Engineering, Andes Technology
As the use of AI is beginning large-scale deployment into our devices, many wonder why specialized AI accelerator is employed, rather
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Whether by talent, art, or black magic, designing RF circuitry is one of the most challenging engineering tasks there is. RF engineers confront a myriad of challenges to bring their designs to life. From the ability to verify a complex 5G standard; running electromagnetic (EM) analysis across chip, package, and board boundaries;
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Thu, Mar 19, 2020 11:00 AM – 12:00 PM MDT
** Work email address required**
Interlaken chip-to-chip connectivity IP has been used for many years in networking and switching fabrics to move high throughput data between large chips. With advanced technology nodes, increasing chip sizes and CPU cluster-based designs, Interlaken
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VLSI 2020 is going virtual!
Given the global health concerns associated with COVID-19 (Coronavirus), the organization of VLSI 2020 has decided to hold the 2020 VLSI Symposia on Technology and Circuits as a virtual conference. Although we will not be meeting in Honolulu this year and it will be impossible to reproduce the lively
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It seems that it has always been that there were packages and ICs, and in the design tool world “never the twain shall meet”. The tools for designing packages were completely separate from the tools used to design IC’s. This was so profoundly true that even after Cadence merged with Valid Logic back in the early 90’s, their Allegro … Read More
PVT – depending on what field you are in those three letters may mean totally different things. In my undergraduate field of study, chemistry, PVT meant Pressure, Volume & Temperature. Many of you probably remember PV=nRT, the dreaded ideal gas law. However, anybody working in semiconductors knows that PVT stands … Read More
When I hear the company name of ANSYS the first EDA tool category that comes to mind is power noise sign-off. Going to DAC is a great way to find out what’s new with EDA, IP and foundries. There are three places that you can find ANSYS at DAC this year:… Read More
In a world with mobile and IoT devices driven by ultra-low power, high performance and small footprint transistors, FinFET based designs are ideal. FinFETs provide high current drive, low leakage and high device density. However, a FinFET transistor is more exposed to thermal issues, electro migration (EM), and electrostatic… Read More
