Tag: chip

Webinar: Maximize Performance and Efficiency of Multi-die Data Center Chip Designs with Arm CoreLink CMN-700 and Synopsys Platform Architect

Webinar: Maximize Performance and Efficiency of Multi-die Data Center Chip Designs with Arm CoreLink CMN-700 and Synopsys Platform Architect
by Admin on 04-09-2023 at 12:53 am

Synopsys Webinar | Wednesday, April 26, 2023 | 10:00 -11:00 a.m. PDT

This webinar will showcase the design, analysis, and optimization of a multi-die fabric architecture based on the next generation Arm® CoreLink™ CMN-700 interconnect, a high-performance cache coherent interconnect solution designed for complex multi-die

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Webinar: How Designing a Custom ASIC Chip Will Help Scientists Detect Neutrinos From Outer Space

Webinar: How Designing a Custom ASIC Chip Will Help Scientists Detect Neutrinos From Outer Space
by Admin on 10-31-2022 at 2:06 pm

Join us on Thursday, November 3rd to learn how Lawrence Berkeley National Laboratory, Fermilab, and Brookhaven National Laboratory collaborated and designed a custom ASIC chip to run at extremely cold temperatures, so that it can detect neutrinos!

Register Today!

Here’s what you can learn:

  • Why study neutrinos and how to detect
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Optimized Chip Design with Main Processors and AI Accelerators

Optimized Chip Design with Main Processors and AI Accelerators
by Admin on 01-26-2022 at 12:19 pm

Feb 15 2022, 10:00am PST

Presented by

Paul Karazuba, VP of Marketing, Expedera & John Min, Director of Field Application Engineering, Andes Technology

About this talk

As the use of AI is beginning large-scale deployment into our devices, many wonder why specialized AI accelerator is employed, rather
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Webinar Series: Thinking Outside the Chip

Webinar Series: Thinking Outside the Chip
by Admin on 06-16-2020 at 6:34 am

Whether by talent, art, or black magic, designing RF circuitry is one of the most challenging engineering tasks there is. RF engineers confront a myriad of challenges to bring their designs to life.  From the ability to verify a complex 5G standard; running electromagnetic (EM) analysis across chip, package, and board boundaries;

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Chip-to-Chip Communication (Interlaken-LL) for Enterprise and Cloud

Chip-to-Chip Communication (Interlaken-LL) for Enterprise and Cloud
by Admin on 03-14-2020 at 2:39 am

Thu, Mar 19, 2020 11:00 AM – 12:00 PM MDT

** Work email address required**
Interlaken chip-to-chip connectivity IP has been used for many years in networking and switching fabrics to move high throughput data between large chips. With advanced technology nodes, increasing chip sizes and CPU cluster-based designs, Interlaken
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2020 Symposia on VLSI Technology and Circuits

2020 Symposia on VLSI Technology and Circuits
by Admin on 02-21-2020 at 12:48 pm

VLSI 2020 is going virtual!

Given the global health concerns associated with COVID-19 (Coronavirus), the organization of VLSI 2020 has decided to hold the 2020 VLSI Symposia on Technology and Circuits as a virtual conference. Although we will not be meeting in Honolulu this year and it will be impossible to reproduce the lively

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At Last, Package and Chip integration for RF Design

At Last, Package and Chip integration for RF Design
by Tom Simon on 01-21-2019 at 7:00 am
Categories: Cadence, EDA

It seems that it has always been that there were packages and ICs, and in the design tool world “never the twain shall meet”. The tools for designing packages were completely separate from the tools used to design IC’s. This was so profoundly true that even after Cadence merged with Valid Logic back in the early 90’s, their Allegro … Read More

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Making AI Silicon Smart with PVT Monitoring

Making AI Silicon Smart with PVT Monitoring
by Tom Simon on 11-26-2018 at 7:00 am
Categories: AI, IP, Moortec

PVT – depending on what field you are in those three letters may mean totally different things. In my undergraduate field of study, chemistry, PVT meant Pressure, Volume & Temperature. Many of you probably remember PV=nRT, the dreaded ideal gas law. However, anybody working in semiconductors knows that PVT stands … Read More