Date: Tuesday, October 18, 2022
North America Session: 9:00am – 10:00am PT
EMEAI Session: 11:00am – 12:00pm CET
Demand for next-generation wireless communication, aerospace, and transportation systems is driving the need for high-performance, cost-sensitive silicon RFICs and III-V compound semiconductor … Read More
Synopsys Webinar | Wednesday, August 17, 2022 | 10:00 a.m. PT
Wireless communication is at the heart of the technological revolution of the past few decades and RF circuits are what enable wireless systems to communicate with each other. The design and characterization of RF circuits is a complex process that requires the designer
Time:
September 13, 2021
8 AM EDT / 1 PM BST / 5:30 PM IST
Venue:
Onlineo
About this Webinar
In today’s near threshold designs, trends like tighter integration and increasing layout density on advanced nodes, frequency escalation (5G) and complex packaging scenarios are making the need for accurate and efficient electromagnetic… Read More
Compute environments have advanced significantly over the past several years. Microprocessors have gotten faster by including more cores, available RAM has increased significantly, and the cloud has made massive distributed computing more easily and cheaply available.
HFSS has evolved to take advantage of these new capabilities,… Read More
June 4, 2020
10:30 AM (EDT)
Venue:
Online
Ansys RaptorH adds to Ansys’ comprehensive set of electromagnetic (EM) field solver modeling capabilities, which extend from devices to chips to full electronics systems. The enhanced on-silicon EM simulation now includes the Ansys HFSS gold-standard engine integrated into an easy-to-use
June 2, 2020
8:30 PM (EDT)
Venue:
Online
Ansys RaptorH adds to Ansys’ comprehensive set of electromagnetic (EM) field solver modeling capabilities, which extend from devices to chips to full electronics systems. The enhanced on-silicon EM simulation now includes the Ansys HFSS gold-standard engine integrated into an easy-to-use
It seems that it has always been that there were packages and ICs, and in the design tool world “never the twain shall meet”. The tools for designing packages were completely separate from the tools used to design IC’s. This was so profoundly true that even after Cadence merged with Valid Logic back in the early 90’s, their Allegro … Read More
RFIC developers used to favor mature silicon processes, typically staying back a couple of nodes behind the leading edge. This bought foundries time for ‘RF-enabling’ their PDKs, and also maximized return on investment for developing RF models and infrastructure IP. Not the case any more, it seems. To address the insatiable … Read More
