Revolutionizing RFIC Design: Introducing RFIC-GPT

Revolutionizing RFIC Design: Introducing RFIC-GPT
by Jason Liu on 02-28-2024 at 6:00 am

Figure1 (10)

In the rapidly evolving world of Radio Frequency Integrated Circuits (RFIC), the challenge has always been to design efficient, high-performance components quickly and accurately. Traditional methods, while effective, come with a high complexity and a lengthy iteration process. Today, we’re excited to unveil RFIC-GPTRead More


Webinar: Cadence Further Streamlines MMIC, RFIC, and RF SiP Design Workflows

Webinar: Cadence Further Streamlines MMIC, RFIC, and RF SiP Design Workflows
by Admin on 09-22-2022 at 2:46 pm

Date: Tuesday, October 18, 2022

North America Session: 9:00am – 10:00am PT

EMEAI Session: 11:00am – 12:00pm CET

Demand for next-generation wireless communication, aerospace, and transportation systems is driving the need for high-performance, cost-sensitive silicon RFICs and III-V compound semiconductor … Read More


Design and Verify State-of-the-Art RFICs using Synopsys / Ansys Custom Design Flow

Design and Verify State-of-the-Art RFICs using Synopsys / Ansys Custom Design Flow
by Admin on 08-10-2022 at 3:24 pm

Synopsys Webinar | Wednesday, August 17, 2022 | 10:00 a.m. PT

Wireless communication is at the heart of the technological revolution of the past few decades and RF circuits are what enable wireless systems to communicate with each other. The design and characterization of RF circuits is a complex process that requires the designer

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De-risking RFICs and High Speed SoCs from Electromagnetic Crosstalk

De-risking RFICs and High Speed SoCs from Electromagnetic Crosstalk
by Admin on 08-11-2021 at 8:30 am

Time:
September 13, 2021
8 AM EDT / 1 PM BST / 5:30 PM IST

Venue:
Onlineo

About this Webinar

In today’s near threshold designs, trends like tighter integration and increasing layout density on advanced nodes, frequency escalation (5G) and complex packaging scenarios are making the need for accurate and efficient electromagnetic… Read More


Best Practices are Much Better with Ansys Cloud and HFSS

Best Practices are Much Better with Ansys Cloud and HFSS
by Daniel Nenni on 02-04-2021 at 6:00 am

Ansys PAM4 PKG

Compute environments have advanced significantly over the past several years. Microprocessors have gotten faster by including more cores, available RAM has increased significantly, and the cloud has made massive distributed computing more easily and cheaply available.

HFSS has evolved to take advantage of these new capabilities,… Read More


Introducing Ansys RaptorH: SoC, Mixed-Signal and RFIC Electromagnetic Modeling

Introducing Ansys RaptorH: SoC, Mixed-Signal and RFIC Electromagnetic Modeling
by Admin on 05-24-2020 at 4:21 am

June 4, 2020

10:30 AM (EDT)

Venue:
Online

Ansys RaptorH adds to Ansys’ comprehensive set of electromagnetic (EM) field solver modeling capabilities, which extend from devices to chips to full electronics systems. The enhanced on-silicon EM simulation now includes the Ansys HFSS gold-standard engine integrated into an easy-to-use

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Introducing Ansys RaptorH: SoC, Mixed-Signal and RFIC Electromagnetic Modeling

Introducing Ansys RaptorH: SoC, Mixed-Signal and RFIC Electromagnetic Modeling
by Admin on 05-24-2020 at 4:15 am

June 2, 2020

8:30 PM (EDT)

Venue:
Online

Ansys RaptorH adds to Ansys’ comprehensive set of electromagnetic (EM) field solver modeling capabilities, which extend from devices to chips to full electronics systems. The enhanced on-silicon EM simulation now includes the Ansys HFSS gold-standard engine integrated into an easy-to-use

Read More

At Last, Package and Chip integration for RF Design

At Last, Package and Chip integration for RF Design
by Tom Simon on 01-21-2019 at 7:00 am

It seems that it has always been that there were packages and ICs, and in the design tool world “never the twain shall meet”. The tools for designing packages were completely separate from the tools used to design IC’s. This was so profoundly true that even after Cadence merged with Valid Logic back in the early 90’s, their Allegro … Read More


RFIC Design Challenges at #50DAC

RFIC Design Challenges at #50DAC
by Daniel Nenni on 05-31-2013 at 8:00 pm

RFIC developers used to favor mature silicon processes, typically staying back a couple of nodes behind the leading edge. This bought foundries time for ‘RF-enabling’ their PDKs, and also maximized return on investment for developing RF models and infrastructure IP. Not the case any more, it seems. To address the insatiable Read More