Concept Modeling: Design Exploration for Every Engineer

Concept Modeling: Design Exploration for Every Engineer
by Admin on 05-12-2020 at 11:00 am

May 12, 2020

11:00 AM (EDT)

Venue:
Online

This webinar will describe how ANSYS Discovery is replacing traditional CAD technologies with direct editing and a modern UI that is fast, easy and intuitive to learn. Discovery can import, repair and modify files from any CAD system, including the native CAD files or the generic files used

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Electronics cooling – accelerated

Electronics cooling – accelerated
by Admin on 05-12-2020 at 10:00 am

ICEPAKDetailed

  

Big challenge of electronics cooling is the geometry complexity we deal with.

In this webinar we demonstrate a number of new features that makes it faster and easier to setup simulations in ANSYS ICEPAK. This is especially true for more complex geometries.

Come and learn the latest tips and

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7 Tips in 17 Minutes | Leveraging CFD for Electronics

7 Tips in 17 Minutes | Leveraging CFD for Electronics
by Admin on 04-21-2020 at 11:00 am

April 21, 2020

11:00 AM (EDT)

Venue:
Online

We’re back at it again in our new Ansys Discovery Webinar Series, now sharing CFD knowledge in under 17 minutes!

KEY TAKEAWAYS:

  • Understanding design trade-offs through CFD Analysis
  • Seven (7) productive tips you can leverage immediately in a CFDr Workflow
  • Learn how you can perform
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Increasing Student Engagement in Materials Education Using Ansys GRANTA EduPack

Increasing Student Engagement in Materials Education Using Ansys GRANTA EduPack
by Admin on 04-21-2020 at 11:00 am

April 21, 2020

11 AM EDT / 3 PM GMT

Venue:
Online

Student engagement is an integral part of teaching. The more ways a student can interact with the course material, the stronger their connection to it. While lectures can be effective for communicating information on any topic to an audience of varying sizes, they often result in low

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Prevent and Eliminate IR drop and Power Integrity Issues using Redhawk Analysis Fusion

Prevent and Eliminate IR drop and Power Integrity Issues using Redhawk Analysis Fusion
by Admin on 03-31-2020 at 11:00 am

Tue, Mar 31, 2020 11:00 AM – 12:00 PM MDT

*** This webinar requires that you register with your work email address ***

As we move towards advanced nodes where supply voltage reduces and transistors shrink in size, reliability challenges increase significantly. Designers see more IR drop and power integrity issues, and we… Read More


Analog IP Migration, Optimization and Verification

Analog IP Migration, Optimization and Verification
by Admin on 03-26-2020 at 11:00 am

Thu, Mar 26, 2020 11:00 AM – 12:00 PM MDT

** Work email address required**

ABSTRACT: Semiconductor companies designing ICs for smart phones, automotive and industrial applications, CPUs, GPUs and memory components all employ teams of custom IC designers to create the highest performance chips that are as small as possible,… Read More


Achieving Design Robustness in Signoff for Advanced Node Digital Designs

Achieving Design Robustness in Signoff for Advanced Node Digital Designs
by Admin on 03-24-2020 at 11:00 am

Tue, Mar 24, 2020 11:00 AM – 12:00 PM MDT

*** This vendor requires that you register with your work email address ***

As designs migrate to cutting edge single digit nanometer technologies, designing high yielding products that quickly enter the market is key to remain competitive in the chip industry. Advanced node digital… Read More


Chip-to-Chip Communication (Interlaken-LL) for Enterprise and Cloud

Chip-to-Chip Communication (Interlaken-LL) for Enterprise and Cloud
by Admin on 03-19-2020 at 11:00 am

Thu, Mar 19, 2020 11:00 AM – 12:00 PM MDT

** Work email address required**
Interlaken chip-to-chip connectivity IP has been used for many years in networking and switching fabrics to move high throughput data between large chips. With advanced technology nodes, increasing chip sizes and CPU cluster-based designs, Interlaken
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Six Automated Steps to Design Partitioning for Multi-FPGA Prototyping Boards

Six Automated Steps to Design Partitioning for Multi-FPGA Prototyping Boards
by Admin on 03-17-2020 at 11:00 am

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Tue, Mar 17, 2020 11:00 AM – 12:00 PM MDT

** Work email address required**
ABSTRACT
Presently, emulation and FPGA-based prototyping are essential verification and validation techniques for a SoC, ASIC designs and become irreplaceable in pre-silicon verification of Deep Learning Accelerator designs. Challenges of
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Webinar: Improving SI/PI Simulation of DDR Interfaces at the PCB/IC Package Level

Webinar: Improving SI/PI Simulation of DDR Interfaces at the PCB/IC Package Level
by Admin on 03-08-2020 at 9:00 am

Double data rate (DDR) synchronous dynamic random-access memory (SDRAM) is the common type of memory used as RAM for almost every modern processor. With DDR memory interface voltages decreasing, speeds increasing, and timing/power budgets being squeezed, design qualification using the latest memory interfaces is no small… Read More