Automating Post-Route Verification for Multi-Gigabit Channels

Automating Post-Route Verification for Multi-Gigabit Channels
by Admin on 09-08-2020 at 10:00 am

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Online – Sep 8, 2020
10:00 AM – 11:00 AM Asia/Singapore
Online – Sep 8, 2020
2:00 PM – 3:00 PM Europe/London
Online – Sep 8, 2020
2:00 PM – 3:00 PM US/Eastern

Overview

Performing post-layout verification of multi-gigabit SerDes channels

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Designing SerDes Channels for Protocol Compliance

Designing SerDes Channels for Protocol Compliance
by Admin on 08-18-2020 at 10:00 am

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Online – Aug 18, 2020
10:00 AM – 11:00 AM Asia/Singapore
Online – Aug 18, 2020
2:00 PM – 3:00 PM Europe/London
Online – Aug 18, 2020
2:00 PM – 3:00 PM US/Eastern

Overview

Multi-gigabit serial channels present some of the most stringent

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HCL Webinar Series – HCL VersionVault Delivers Version Control and More

HCL Webinar Series – HCL VersionVault Delivers Version Control and More
by Mike Gianfagna on 08-06-2020 at 10:00 am

Screen Shot 2020 08 02 at 9.23.20 PM

HCL is an interesting organization. You may know them as an Indian company that provides software and hardware services.  At about $10B US and over 110,000 employees working around the world, they are indeed a force in the industry. They’ve also created a software company called HCL Software that develops tools and technologies… Read More


A Hybrid Design Verification Methodology for Increased Coverage and Faster Iterations

A Hybrid Design Verification Methodology for Increased Coverage and Faster Iterations
by Admin on 07-28-2020 at 2:00 pm

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Register For This Web Seminar

Online – Jul 28, 2020
2:00 PM – 3:00 PM Europe/London
Online – Jul 28, 2020
2:00 PM – 3:00 PM US/Eastern

Overview

70% of signals in today’s PCB designs require layout constraints for high-speed signaling, EMI, or safety requirements. Proper implementation

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Tessent SiliconInsight ATE-Connect: Bending the bring up schedule curve in your favor

Tessent SiliconInsight ATE-Connect: Bending the bring up schedule curve in your favor
by Admin on 07-28-2020 at 8:00 am

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Online – Jun 16, 2020
5:00 PM – 6:00 PM US/Pacific
Online – Jul 28, 2020
8:00 AM – 9:00 AM US/Pacific

Overview

With  the number of IP blocks and complexity of designs increasing, how do you improve your TTM for debug of a test program to production?  Teradyne

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Valor Process Preparation Webinar – A Single Engineering Solution

Valor Process Preparation Webinar – A Single Engineering Solution
by Admin on 07-15-2020 at 11:00 am

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Register For This Web Seminar

Online – Jul 15, 2020
11:00 AM – 12:00 PM US/Pacific

Overview

Valor Process Preparation – A Single Engineering Solution for PCB Assembly and Test

Electronics manufacturers typically have a silo system in which they perform the PCB assembly process engineering. The main

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Tessent DDYA – Improving the throughput of volume scan diagnosis by 10X using dynamic partitioning

Tessent DDYA – Improving the throughput of volume scan diagnosis by 10X using dynamic partitioning
by Admin on 07-14-2020 at 5:00 pm

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Online – Jul 14, 2020
5:00 PM – 6:00 PM US/Pacific
Online – Jul 15, 2020
8:00 AM – 9:00 AM US/Pacific

Overview

Learn how to achieve efficient utilization of hardware resources for volume scan diagnosis. This web seminar will be conducted by an expert in design-for-test

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From Simulink to High-Quality RTL using High-Level Synthesis — The Design Methodology

From Simulink to High-Quality RTL using High-Level Synthesis — The Design Methodology
by Admin on 07-14-2020 at 10:00 am

Register For This Web Seminar

Online – Jul 14, 2020
10:00 AM – 11:00 AM US/Pacific

Overview

Nowadays many ASIC and FPGA design projects start with a Simulink reference model. The traditional path from an abstract floating-point Simulink model to high-quality RTL code is long and often requires multiple

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Active Learning for Fast, Comprehensive SPICE Verification

Active Learning for Fast, Comprehensive SPICE Verification
by Admin on 07-08-2020 at 8:00 am

Register For This Web Seminar

Online – Jul 8, 2020
8:00 AM – 9:00 AM US/Pacific
Online – Jul 8, 2020
5:00 PM – 6:00 PM US/Pacific

Overview

The scope of SPICE-level verification has increased massively with new requirements for safety critical applications, statistical timing characterization,

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WEBINAR: ACCELERATE DESIGN PRODUCTIVITY WITH VIRTUOSO ADE EXPLORER AND ASSEMBLER

WEBINAR: ACCELERATE DESIGN PRODUCTIVITY WITH VIRTUOSO ADE EXPLORER AND ASSEMBLER
by Admin on 07-08-2020 at 12:00 am

With the emergence of new ISO standards, advanced-node designs, and system design

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