Edge AI is rapidly transforming how intelligent solutions are designed, from smart home devices to autonomous vehicles, healthcare gadgets, and industrial IoT. Yet, architects, chip designers, and product managers frequently grapple with a common and daunting challenge: creating efficient, high-performance AI solutions… Read More
In today’s data-driven systems—from cloud storage and AI accelerators to automotive logging and edge computing—every byte counts. The exponential growth in data volumes, real-time processing demands, and constrained bandwidth has made efficient, lossless data compression a mission-critical requirement. Software-based… Read More
We’ll dive into one of the most pressing questions in the community:
Are physical attacks practical against post-quantum schemes in the real world? If yes, how to harden the code or the hardware?
How can cryptographic algorithms and their implementations be targeted by physical attacks?
Leveraging… Read More
As AI workloads increasingly dominate numerous cloud and edge applications, building a scalable, efficient, and future-ready AI chips is no longer optional—it’s essential. This webinar explores the latest AI trends, highlighting the growing demand for intelligent processing closer to the data source and
Thursday, July 10, 2025
10:00am PDT | 1:00pm EDT | 19:00 CEST
As AI revolutionizes industries, the demand for high-performance, low power computing intensifies, placing unprecedented requirements on data centers. This panel will explore the transformative impact of AI processing on data center reliability, availability,… Read More
This workshop is for hardware engineers, system architects, and anyone who wants to learn best practices for debugging challenging issues encountered while developing FPGAs, SoCs, PCBs, and embedded systems using the Vivado Design Suite. The features and capabilities of the Vivado
Clock domain crossings (CDCs) are a critical aspect of FPGA and embedded system design, and handling them correctly is essential for reliable operation. In this one-hour webinar, we’ll break down CDC fundamentals, explore best practices for managing single-bit and bus CDCs, and demonstrate how to leverage Xilinx… Read More
Do you struggle to identify which constraints are needed for a design or how to properly input them? This workshop will cover how to use features in Vivado, clock domain crossing strategies, and how to get the most out of static timing analysis for Versal devices.
This… Read More
BLT, an AMD Premier Design Services Partner and Authorized Training Provider, presents this webinar.
Unlock the potential of the AMD Kria SOM and discover Time-Sensitive Networking (TSN) benefits for your applications. In this session, you’ll explore the TSN-ROS application and its role in enhancing communications… Read More
Do you find it challenging to close timing in your FPGA design? This workshop will guide you through leveraging AMD Vivado’s tools, optimizing your design, and applying best practices for static timing analysis to achieve reliable timing closure.
Gain hands-on experience … Read More
