This workshop introduces the AMD Versal network on chip (NoC) to users familiar with other SoC architectures. Besides providing an overview of the major components in the Versal device, the course illustrates how the NoC is used to efficiently move
BLT, an AMD Premier Design Services Partner and Authorized Training Provider, presents this webinar.
Join us to explore the functionality and configurability of the AMD Zynq UltraScale+ RFSoC. With the RFSoC, configuring data converters is crucial for advanced system development, but the complexity often overwhelms… Read More
This workshop covers the AMD Versal AI Engine architecture and using the AI Engine DSP Library, system partitioning, rapid prototyping, and custom coding of AI Engine kernels. Developing AI Engine DSP designs using AMD Vitis Model Composer is also demonstrated.
The
BLT, an AMD Premier Design Services Partner and Authorized Training Provider, presents this webinar.
Are FPGA booting challenges causing frustrating delays and leaving you uncertain about project timelines? Have you spent countless hours wrestling with boot image creation, only to encounter hardware dependencies… Read More
This online workshop introduces key concepts, tools, and techniques required for design and development using the AMD Vivado™ Design Suite for FPGAs, SoCs, and adaptive SoCs.
BLT, an AMD Premier Design Services Partner and Authorized Training Provider, presents this webinar.
Are you struggling to bridge the gap between high-level algorithm design and efficient FPGA implementation? Integrating High-Level Synthesis (HLS) into your Vivado block designs can be a game changer, but many… Read More
This workshop provides a foundational introduction to digital logic, tailored for beginners and professionals who want to understand the principles of digital design.
The emphasis of this course is on:
Overview of the design of today’s complex chips with Electronic Design Automation tools.
June 25, 2025 | 10:00am-11:30am PT
Complex semiconductor chips power today’s cell phones, cars, computers, and more. This on-line Master Class will provide non-technical people who work in and around the chip design industry a high-level
IR signoff for advanced SoCs and 3D-ICs is a major challenge due to extremely large and complex power networks that can exceed 100 billion nodes. Designers are faced with very long runtimes and very large compute resource requirements amounting to thousands of CPUs and 100TB+ memory to run a full-chip flat.
In this
Are you ready to disrupt decades of outdated processes and lead a smarter, more sustainable future in semiconductor manufacturing? While the digital twin has long been a cornerstone of chip design, its power has yet to be fully harnessed on the fab floor. Meanwhile, manufacturers experience increased pressure
