IR signoff for advanced SoCs and 3D-ICs is a major challenge due to extremely large and complex power networks that can exceed 100 billion nodes. Designers are faced with very long runtimes and very large compute resource requirements amounting to thousands of CPUs and 100TB+ memory to run a full-chip flat.
In this
Are you ready to disrupt decades of outdated processes and lead a smarter, more sustainable future in semiconductor manufacturing? While the digital twin has long been a cornerstone of chip design, its power has yet to be fully harnessed on the fab floor. Meanwhile, manufacturers experience increased pressure
DATE: Wednesday, June 18, 2025
TIME: 8:00am PDT | 11:00am EDT | 3:00pm GMT | 8:30pm IST
Experience the future of Engineering BOM Management with OrCAD X. Our innovative Live BOM feature revolutionizes your design and supply chain processes, empowering your projects with unmatched visibility, optimization, and control.
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Join us for an insightful webinar where we delve into the latest advancements in Synopsys ARC Processor IP, designed to meet the stringent demands of real-time processing systems across industries. Gain valuable knowledge
The increasing complexity of chip designs that leverage 3D-IC technology, heterogeneous integration, and other manufacturing advancements, emphasizes the need for accurate modeling of electromagnetic (EM) crosstalk. EM solvers continue to play a key role in solving larger problems both in terms of layout
June 12, 2025 | 10:00 AM PDT
1 Hour
Artificial intelligence and machine learning (AI/ML) are revolutionizing wireless communications, creating opportunities for innovation and greater efficiency in the communication landscape. However, designing and testing AI/ML algorithms for dynamic and complex wireless environments
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As AI systems become increasingly vital across industries, ensuring their security and integrity is more critical – and challenging – than ever.
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This webinar introduces Questa One Sim CX, an innovative coverage-driven simulation solution that revolutionizes SystemVerilog UVM verification workflows.
Traditional coverage closure methods, relying on constrained-random stimulus generation and iterative manual adjustments, often prove time-consuming and resource-intensive.
Rising semiconductor complexity—driven by multi-die architectures, the move towards more advanced technology nodes, and more stringent reliability targets, is dramatically increasing the volume of verification required to achieve DFT verification sign-off.
Come learn how the Questa One DFT Verification solution, combined
Wednesday, June 4 – 8:00 AM Pacific
In today’s automotive electronics, ensuring functional safety is paramount for meeting stringent industry standards. This webinar introduces Questa One Sim FX, a cutting-edge fault simulation platform designed specifically for complex automotive designs. We’ll
