Webinar: Reimagining Synopsys SLM PVT Monitoring IP for Advanced Node GAA Process

Webinar: Reimagining Synopsys SLM PVT Monitoring IP for Advanced Node GAA Process
by Admin on 05-10-2024 at 2:15 pm

Synopsys’ SLM PVT Monitor (process detector, voltage monitor, temperature sensor) IP can collect voltage, temperature, and process parameters from different blocks within the IC in real time. These data can be analyzed and used to take meaningful action to optimize the performance of the chip at any stage of silicon lifecycle.

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Agile Analog Visit at #60DAC

Agile Analog Visit at #60DAC
by Daniel Payne on 07-31-2023 at 10:00 am

agile analog 60dac min

Chris Morrison, Director of Product Marketing at Agile Analog met with me on the Tuesday at DAC this year, and I asked what has changed in the last year for their analog IP business. The short answer is that the company has initially built up foundation IP for Analog Mixed-Signal (AMS) uses, then recently added new IP for data conversion,… Read More


Automotive IP Certification

Automotive IP Certification
by Daniel Payne on 06-05-2023 at 10:00 am

SLM min

The electrification of cars and the growth of EVs means that more semiconductor content is being added with every new vehicle model from suppliers around the globe. There are unique concerns for automotive IP in terms of reliability, security and safety over the lifetime of the vehicle. I had the pleasure to speak with Pawini MahajanRead More


Analog Bits and SEMIFIVE is a Really Big Deal

Analog Bits and SEMIFIVE is a Really Big Deal
by Daniel Nenni on 03-28-2022 at 6:00 am

SemiFive Analog Bits SemiWiki

Given the recent acquisitions the ASIC business is coming full circle as a critical part of the fabless semiconductor ecosystem. The most recent one being the SEMIFIVE acquisition of IP industry stalworth Analog Bits. These two companies came to the industry from opposite directions which make them a perfect match, absolutely.… Read More


Webinar: AMS, RF and Digital Full Custom IC Designs need Circuit Sizing

Webinar: AMS, RF and Digital Full Custom IC Designs need Circuit Sizing
by Daniel Payne on 01-02-2022 at 10:00 am

circuit sizing min

My career started out by designing DRAM circuits at Intel, and we manually sized every transistor in the entire design to get the optimum performance, power and area. Yes, it was time consuming, required lots of SPICE iterations and was a bit error prone. Thank goodness times have changed, and circuit designers can work smarter … Read More


High Reliability Power Management Chip Simulation and Verification for Automotive Electronics

High Reliability Power Management Chip Simulation and Verification for Automotive Electronics
by Daniel Payne on 10-11-2021 at 10:00 am

iWave waveform min

Automotive electronics bring strong demand for power management chips, but its strict reliability requirements also pose new challenges for chip designers. The chip needs to be able to work in various harsh environments such as high temperature, low temperature, aging, abnormal power supply, etc. Although the traditional… Read More


Free Webinar: Analog Verification with Monte Carlo, PVT Corners and Worst-Case Analysis

Free Webinar: Analog Verification with Monte Carlo, PVT Corners and Worst-Case Analysis
by Tom Simon on 04-29-2019 at 4:00 pm

The letters “PVT” roll of the tongue easily enough, belying the complexity that variations in process, temperature and voltage can cause for analog designs. For semiconductor processes, there are dozens of parameters that can affect the viability of a design. It would be easy enough to optimize a circuit with only one or two varying… Read More


Analog IC design across PVT conditions, something new

Analog IC design across PVT conditions, something new
by Daniel Payne on 08-30-2018 at 12:00 pm

Transistor-level design for full-custom and analog circuits has long been a way for IC design companies to get the absolute best performance out of silicon and keep ahead of the competition. One challenge to circuit designers is meeting all of the specs across all Process, Voltage and Temperature (PVT) corners, so that silicon… Read More


Improving Yield and Reliability with In-Chip Monitoring, there’s an IP for that

Improving Yield and Reliability with In-Chip Monitoring, there’s an IP for that
by Daniel Payne on 08-24-2018 at 12:00 pm

There’s an old maxim that you can only improve what you measure, so quality experts have been talking about this concept for decades and our semiconductor industry has been the recipient of such practices to such an extent that we can now buy consumer products that include chips with over 5 billion transistors in them. You’ve… Read More


Monitoring Process, Voltage and Temperature in SoCs, webinar recap

Monitoring Process, Voltage and Temperature in SoCs, webinar recap
by Daniel Payne on 04-26-2018 at 4:00 pm

Have you ever wondered how process variation, thermal self-heating and Vdd levels affect the timing and yield of your SoC design? If you’re clock specification calls for 3GHz, while your silicon is only yielding at 2.4GHz, then you have a big problem on your hands. Such are the concerns of many modern day chip designers. To… Read More