Free Webinar: Analog Verification with Monte Carlo, PVT Corners and Worst-Case Analysis

Free Webinar: Analog Verification with Monte Carlo, PVT Corners and Worst-Case Analysis
by Tom Simon on 04-29-2019 at 4:00 pm

The letters “PVT” roll of the tongue easily enough, belying the complexity that variations in process, temperature and voltage can cause for analog designs. For semiconductor processes, there are dozens of parameters that can affect the viability of a design. It would be easy enough to optimize a circuit with only one or two varying… Read More


Schematic porting – the key to analog design reuse

Schematic porting – the key to analog design reuse
by Tom Simon on 04-02-2018 at 12:00 pm

At the beginning of every project the one of the first questions that ought to be asked is whether there blocks from previous designs that can be reused. On the surface this seems pretty obvious. The wrinkle in this is that reusability varies a lot based on the design type and the effort that a team is willing to expend to bring a design… Read More


Using Sequential Testing to Shorten Monte Carlo Simulations

Using Sequential Testing to Shorten Monte Carlo Simulations
by Tom Simon on 12-27-2017 at 7:00 am

When working on an analog design, after initial design specs have been met, it is useful to determine if the design meets specs out to 3 or 4 sigma based on process variation. This can serve as a useful step before going any further. It might not be a coincidence that foundries base their Cpk on 3-sigma. To refresh, Cpk is the ratio of the… Read More


Seeking Solution for Saving Schematics?

Seeking Solution for Saving Schematics?
by Tom Simon on 11-24-2017 at 7:00 am

Schematics are still the lynchpin of analog design. In the time that HDL’s have revolutionized digital design, schematics have remained drawn and used much as they have been for decades. While the abstraction of HDL based designs has made process and foundry porting relatively straightforward, porting schematic based designs… Read More


Customizable Analog IP No Longer a Pipe Dream

Customizable Analog IP No Longer a Pipe Dream
by Tom Simon on 08-28-2017 at 12:00 pm

Configurable analog IP has traditionally been a tough nut to crack. Digital IP, of course, now provides for wide configurability for varying applications. In the same way that analog design has remained less deterministic as compared to digital design, analog IP has also tended to be less flexible. However, the tide may be turning… Read More


Webinar – Low Power Circuit Sizing for IoT

Webinar – Low Power Circuit Sizing for IoT
by Tom Simon on 05-19-2017 at 7:00 am

Optimizing analog designs has always been a difficult and tricky process. Designing for IoT applications has only made this more difficult with the added importance of minimizing power. Unlike other circuit parameters, it is not easy to specify power as a design goal when using equations. Power is a resultant property and must… Read More


Analog, Low-power Optimization at SMIC

Analog, Low-power Optimization at SMIC
by Daniel Payne on 01-11-2017 at 12:00 pm

Talking with actual IC designers is always fascinating to me, because these engineers are the unsung heroes that enable our modern day world of consumer and industrial electronics. Too often we only hear from the CEO or other C-level executives in the press about their own companies, products, services and vision. I recently had… Read More


Three Steps for Custom IC Design Migration and Optimization

Three Steps for Custom IC Design Migration and Optimization
by Daniel Payne on 08-31-2016 at 7:00 am

Popular companies designing smart phones, CPUs, GPUs and Memory components all employ teams of custom IC designers to create the highest performance chips that are as small as possible, and at the lowest costs. How do they go about doing custom IC design migration and optimization when moving from one process node to another one?… Read More


SRAM Optimization for 14nm and 28nm FDSOI

SRAM Optimization for 14nm and 28nm FDSOI
by Daniel Payne on 05-16-2016 at 4:00 pm

I’ve done SRAM and DRAM design before as a circuit designer from 1978-1986, but in 2016 there are so many more challenges to using 28nm and 14nm on FDSOI technology. One way to keep abreast of SRAM design is to read conference papers, so I just finished a paper from authors at STMicroelectronics and MunEDA presented at the IEEE… Read More


IC Design Optimization for Radiation Hardening

IC Design Optimization for Radiation Hardening
by Daniel Payne on 03-28-2016 at 7:00 am

I was born in 1957, the same year that the Soviets launched the first satellite into Earth orbit, officially starting the Space Race between two global super powers. Today there are many countries engaged in space research and I just read about how engineers at IEAv (Institute for Advanced Studies) in Brazil did their IC design optimization… Read More