Webinar: Synopsys RF / mmWave IC Design Reference Flow with TSMC N6RF and N16FFC Process Nodes

Webinar: Synopsys RF / mmWave IC Design Reference Flow with TSMC N6RF and N16FFC Process Nodes
by Admin on 04-19-2023 at 1:30 pm

Synopsys Webinar | Wednesday, May 10, 2023 | 10:00 a.m. PDT

Wireless devices are ubiquitous, all requiring RF ICs to transmit and receive radio waves via antennas. The radio range can be a few meters for applications such as Bluetooth and WiFi to many kilometers for long range 5G, satellite and radar applications. Today’s

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Webinar: Democratizing IC Design: The IEEE SSCS PICO Program

Webinar: Democratizing IC Design: The IEEE SSCS PICO Program
by Admin on 01-09-2023 at 2:07 pm

Presenter: Boris Murmann

Description

Abstract: Inspired by the possibilities of open-source chip design, the IEEE Solid-State Circuits Society (SSCS) launched its new Platform for IC Design Outreach (PICO) in the summer of 2021. With this program, the SSCS intends to contribute to the new open source movement, forge connections… Read More


What’s the Recipe for Efficient Analog IC Design and Verification?

What’s the Recipe for Efficient Analog IC Design and Verification?
by Admin on 05-17-2021 at 11:52 am

Overview

For analog IC designers, the most important capability is rapid simulation of an accurate model of their circuits. Early in the design process, they explore architectures and novel approaches and need an agile simulation flow that gives them confidence that the implemented design is capable of meeting the system specs.

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Webinar: Designing Methodologies for Next-Generation Heterogeneously Integrated 2.5- and 3D-IC Designs

Webinar: Designing Methodologies for Next-Generation Heterogeneously Integrated 2.5- and 3D-IC Designs
by Admin on 06-16-2020 at 6:35 am

Overview

After years of steady SoC and ASIC aggregation packing functionality into a large single die, the semiconductor industry can no longer meet growing performance demands. In the face of power, performance, and area constraints and reticle limits, and with the cost of production at advanced nodes skyrocketing, there

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DAC 2020 – Call for Contributions

DAC 2020 – Call for Contributions
by Daniel Payne on 10-28-2019 at 6:00 am

57DAC in SFO

My first DAC was in 1987 so I’ve seen our industry expand greatly over the years, and I expect that #57DAC on July 19-23, 2020 in SFO to be another exciting event to attend for semiconductor professionals from around the globe. What makes DAC so compelling for me to visit are the people, exhibitors, panel discussions, technical… Read More


Analog IC design across PVT conditions, something new

Analog IC design across PVT conditions, something new
by Daniel Payne on 08-30-2018 at 12:00 pm

Transistor-level design for full-custom and analog circuits has long been a way for IC design companies to get the absolute best performance out of silicon and keep ahead of the competition. One challenge to circuit designers is meeting all of the specs across all Process, Voltage and Temperature (PVT) corners, so that silicon… Read More


Approaches for EM, IR and Thermal Analysis of ICs

Approaches for EM, IR and Thermal Analysis of ICs
by Daniel Payne on 04-26-2017 at 12:10 pm

As an engineer I’ve learned how to trade off using various EDA tools based on the accuracy requirements and the time available to complete a project. EDA vendors have been offering software tools to help us with reliability concerns like EM, IR drop and thermal analysis for several years now. Last week I attended a webinar … Read More


Why is Low Frequency Noise Measurement for ICs Such a Big Deal?

Why is Low Frequency Noise Measurement for ICs Such a Big Deal?
by Daniel Payne on 09-27-2016 at 12:00 pm

Even digital designers need to be aware of how noise impacts their circuits because most clocked designs today use a Phase Locked Loop (PLL) block which contains a circuit called a Voltage Controlled Oscillator (VCO) that is quite sensitive in operation to the effects of noise and process variation. As process node scaling continues… Read More


Three Steps for Custom IC Design Migration and Optimization

Three Steps for Custom IC Design Migration and Optimization
by Daniel Payne on 08-31-2016 at 7:00 am

Popular companies designing smart phones, CPUs, GPUs and Memory components all employ teams of custom IC designers to create the highest performance chips that are as small as possible, and at the lowest costs. How do they go about doing custom IC design migration and optimization when moving from one process node to another one?… Read More


Low Frequency Noise Challenges IC Designs

Low Frequency Noise Challenges IC Designs
by Daniel Payne on 08-28-2016 at 7:00 am

AMS and RF IC designers have known for years that their circuits are sensitive to noise, because if you amplify noise on an input source to an amplifier circuit then your chip can start to produce wrong answers. Even digital SoC designers need to start taking notice because every SoC is filled with SRAM IP blocks, and at each shrinking… Read More