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A new world of 10nm design constraints

A new world of 10nm design constraints
by Beth Martin on 08-30-2016 at 4:00 pm

Every time the industry transitions to a smaller process node IC design software undergoes extensive updates.

I talked to a couple of experts in physical design at Mentor Graphics about what is involved in making place-and-route software ready for a new node. This is what I learned from Sudhakar Jilla, the IC design marketing director and Benny Winefeld, a senior product engineering manager. They said that for digital place and route software to deal with the new and more complex routing rules, changes had typically involved upgrades to the router and DRC checker. However the introduction of new constraint types, such as implant (submetal) rules, started to cause a direct impact on other place and route subsystems.

Physical violations that emerge right after the placement and legalization stages can be roughly classified into two major categories:

  • DRC errors on submetal layers, such as implants, including:

    • Width, spacing, and area DRC on implant layers
    • Jog rules, typically on Oxide Diffusion (transistor active area) layer
    • Prohibited Drain-Drain abutment

  • Problems on metal and via layers, including:

    • Direct DRC violations, including same mask spacing, between ports or blockages of adjacent lib cells
    • Violations between lib cell ports or blockages and preroutes, such as wires and vias in the power/ ground grid
    • Unroutable cell ports
    • Pin alignment and track color matching

To see a detailed description of the new constraints and how they affect various place and route engines download Mentor’s new whitepaper Understanding Physical Design Constraints in the 10nm Era.

Here are few examples:

Submetal rules—width, spacing, and area
In the most basic of scenarios, standard cells contain just two shapes onsubmetal layers, dividing the cell vertically in half—one half for N implanted area, another for P. These shapes are usually expressed in LEF files as blockages and are often called implant layers. If such a submetal shape is too small then it is flagged as a DRC violation (Fig 1).

Submetal rules—oxide diffusion jogs
Some 16/14nm technology flavors added two new types of submetal rules: minimum-jog and drain-drain abutment. Min-jog violations usually apply to the oxide diffusion (OD) layer (Fig 2).

The placer can fix this by inserting a matching cell to the cell in the middle or inserting a gap that will later be filled (Fig 3).

Metal and via layer rules—pin access and direct DRC with preroutes
Pin access problems are not fundamentally new but are becoming more common. The figure below (Fig 4) shows a cut-spacing violation. The placer should be able to avoid this violation without running a full DRC during every cell move.


Abutted cells can also cause pin blockages, but you don’t want to deploy a blanket prohibition of abutment between all cluster members. Mentor’s place and route tool, Nitro-SoC, takes a statistical/analytical approach and uses soft constraints to improve routability.

Metal and via layer rules—Pin-to-track color matching
This is a new placement constraint that emerged at 10nm because of self-aligned double patterning . It has a direct impact on cell placement as cell ports must be centered on a routing track and the mask and track colors must match. Routing pitch is not always equal to the 2x site width, so a cell can easily land in locations where ports will either miss the track or will be on the opposite color (Fig 5).

Nitro-SoC placer can figure out the discrete subset of legal locations for each library cell that will guarantee alignment and mask matching between cell ports and routing tracks.

For technologies with triple-patterned M1, required same mask M1 spacing is very large. Both spreading cells and designing cells to prevent triple-pattern conflicts are too conservative. Instead, Nitro-SoC uses hybrid approach of swapping masks wherever possible. This means that the placer will replace a cell with its “mirror” variant, where M1 mask1 shapes become mask2 and vice versa. Because is not an actual cell movement it has no impact on routability or timing. Only those violations that can’t be cured with mask swapping are repaired with spreading.

If you want far more details and examples of violations at 10nm and below and how they are handled during physical implementation, download the new whitepaper Understanding Physical Design Constraints in the 10nm Era.