Checking and Fixing Antenna Effects in IC Layouts

Checking and Fixing Antenna Effects in IC Layouts
by Daniel Payne on 03-14-2024 at 10:00 am

Planar CMOS cross-section – antenna DRC

IC layouts go through extensive design rule checking to ensure correctness, before being accepted for fabrication at a foundry or IDM. There’s something called the antenna effect that happens during chip manufacturing where plasma-induced damage (PID) can lower the reliability of MOSFET devices. Layout designers run Design… Read More


Soft checks are needed during Electrical Rule Checking of IC layouts

Soft checks are needed during Electrical Rule Checking of IC layouts
by Daniel Payne on 02-28-2024 at 10:00 am

Metal1 Via Metal2 s

IC designs have physical verification applications like Layout Versus Schematic (LVS) at the transistor-level to ensure that layout and schematics are equivalent, in addition there’s an Electrical Rules Check (ERC) for connections to well regions called a soft check. The  connections to all the devices needs to have the most… Read More


Webinar: Finding Hidden Treasures to Accelerate Routing Your Layout

Webinar: Finding Hidden Treasures to Accelerate Routing Your Layout
by Admin on 02-26-2024 at 7:42 pm

Webinar Series: What’s New About Virtuoso Layout Suite

How can you get the most out of your Virtuoso layout tools? How much do you know about the new layout features in Virtuoso Studio? Join our four-part webinar series and learn how Cadence has reinvented the industry-leading Virtuoso Layout Suite, supporting heterogeneousRead More


Webinar: Save on Signoff Effort with In-Design DRC and Fill

Webinar: Save on Signoff Effort with In-Design DRC and Fill
by Admin on 02-26-2024 at 7:38 pm

Webinar Series: What’s New About Virtuoso Layout Suite

How can you get the most out of your Virtuoso layout tools? How much do you know about the new layout features in Virtuoso Studio? Join our four-part webinar series and learn how Cadence has reinvented the industry-leading Virtuoso Layout Suite, supporting heterogeneousRead More


Successful 3DIC design requires an integrated approach

Successful 3DIC design requires an integrated approach
by Kalar Rajendiran on 11-13-2023 at 6:00 am

Siemens EDA 3DIC Graphics

While the leap from traditional SoC/IC designs to Three-Dimensional Integrated Circuits (3DICs) designs brings new benefits and opportunities, it also introduces new challenges. The benefits include performance, power efficiency, footprint reduction and cost savings. The challenges span design, verification, thermal… Read More


Unlock first-time-right complex photonic integrated circuits

Unlock first-time-right complex photonic integrated circuits
by Raha Vafaei on 06-01-2022 at 10:00 am

EPDA overview

The capacity and energy efficiency challenges from the growing appetite for high-speed data along with advanced applications such as LIDAR and quantum computing are driving demand for increasingly large-scale photonic integrated circuits (PIC). With an ever-increasing number of components on a single photonic chip, manual… Read More


EDA in the Cloud – Now More Than Ever

EDA in the Cloud – Now More Than Ever
by Kalar Rajendiran on 07-27-2021 at 10:00 am

Screen Shot 2021 07 14 at 4.32.16 PM

A decade ago, many of us heard commentaries on how entrepreneurs were turned down by venture capitalists for not including a cloud strategy in their business plan, no matter what the core business was. Humorous punchlines such as, “It’s cloudy without any clouds” and “Add some cloud to your strategy and your future will be bright… Read More


RealTime Digital DRC Can Save Time Close to Tapeout

RealTime Digital DRC Can Save Time Close to Tapeout
by Tom Simon on 06-07-2021 at 6:00 am

RealTime DRC

Over the years DRC tools have done an admirable job of keeping pace with the huge growth of IC design size. Yet, DRC runs for sign off on the full design using foundry rule decks take many hours to complete. These long run times are acceptable for final sign off, but there are many situations where DRC results are needed quickly when small… Read More


Analysis of Curvilinear FPDs

Analysis of Curvilinear FPDs
by Daniel Payne on 12-31-2020 at 6:00 am

FPD voltage distribution analysis min

This area of automating the design of Flat Panel Displays (FPD) is so broad that it has taken me three blogs to cover all of the details, so in brief review the first two blogs were:

My final blog covers five areas:

  • DRC/LVS for curvilinear layout
  • Circuit
Read More

Calibre Commences Cloud Computing

Calibre Commences Cloud Computing
by Tom Simon on 11-06-2019 at 10:00 am

Calibre was a big game changer for DRC users when it first came out. Its hierarchical approach dramatically shortened runtimes with the same accuracy as other existing, but slower, flat tools. However, one unsung part of this story was that getting Calibre up and running required minimal effort for users. Two things are required… Read More