Latest Pinpoint release tackles DRC and trend lines

Latest Pinpoint release tackles DRC and trend lines
by Don Dingee on 07-06-2016 at 4:00 pm

After reading previous SemiWiki coverage on Dassault Systèmes and their ENOVIA Pinpoint solution, one big item seemed missing: how does this thing actually work? With all due respect to our other bloggers who covered when Dassault Systèmes acquired Pinpoint from Tuscany Design Automation, why Qualcomm is using Pinpoint, and… Read More


The Young and the Restless, PDA vs EDA, Photonic Soaps continued…

The Young and the Restless, PDA vs EDA, Photonic Soaps continued…
by Mitch Heins on 06-16-2016 at 7:00 am

Image RemovedIf you’ve followed my last article, The Guiding Light and Other Photonic Soaps, you read my comments about the use of waveguides to “guide the light” in photonic integrated circuits (PICs). This article continues the soap opera theme, this time with the Young and the Restless. My point here is that I am continually … Read More


DRC Concept for IP Qualification and SoC Integration

DRC Concept for IP Qualification and SoC Integration
by Pawan Fangaria on 05-30-2016 at 7:00 am

In the history of semiconductor design and manufacturing, the age-old concept of DRC rule-deck qualification for handshake between design and manufacturing still applies strongly to produce working silicon. In fact, DRC clean GDSII works as the de facto golden gate between a design and a foundry for manufacturing the chip for… Read More


Calibre in the Middle of Semiconductor Ecosystem

Calibre in the Middle of Semiconductor Ecosystem
by Pawan Fangaria on 12-20-2015 at 12:00 pm

Albert Einsteinhad said, “In the middle of difficulty lies opportunity”. In today’s world dominated by technology, or I must say internet which has initiated collaborative information sharing, “leading from the middle” is the new mantra of life.… Read More


Together At Last—Combining Netlist and Layout Data for Power-Aware Verification

Together At Last—Combining Netlist and Layout Data for Power-Aware Verification
by Beth Martin on 09-25-2015 at 12:00 pm

The market demanded that gadgets it loves become ever more conscious of their power consumption, and chip designers responded with an array of clever techniques to cut IC power use. Unsurprisingly, these new techniques added to the complexity of IC verification. When you’re verifying a design that has 100+ separate power domains,… Read More


For high-volume manufacturing at 10 nm and below: technology and friendship

For high-volume manufacturing at 10 nm and below: technology and friendship
by Beth Martin on 09-03-2015 at 4:00 pm

The technology for 10 nm is settled, but what about 7 nm and 5 nm? Those nodes will happen with silicon-based CMOS and 193nm immersion lithography, but exactly how is still being worked out. Right now, though, the focus is on getting 10 nm chips into high-volume production. TSMC and Intel both claim to be on track for high-volume manufacturing… Read More


Automate those voltage-dependent DRC checks!

Automate those voltage-dependent DRC checks!
by Beth Martin on 06-04-2015 at 10:00 pm

Because IC design and verification never gets simpler, verification engineers now have to comply with voltage-dependent DRC (VD-DRC) rules. What does this term mean, and what new challenges does it bring to the DRC task? I’d like to share what I learned during another water-cooler conversation with Dina Medhat, senior technical… Read More


How Good is Your DRC Deck?

How Good is Your DRC Deck?
by Daniel Nenni on 05-24-2015 at 4:30 pm

Design Rule Check (DRC) is the #1 foundry sign-off check. Fabless companies receive the DRC deck from the foundry; it’s a file comprising thousands of commands in a proprietary checker language for a specific DRC tool. In advanced technologies such a deck executes tens of thousands of geometric operations on the physical… Read More


Accelerate Modern PCB Design and Manufacturing

Accelerate Modern PCB Design and Manufacturing
by Pawan Fangaria on 05-24-2015 at 12:00 pm

In modern electronic industry PCBs are required to accommodate highly dense circuits with large number of components and complex routing spaces. While the complexity is increasing, the time-to-market is decreasing. In such a scenario, there is no other option than to reduce the design time by employing innovative editing options… Read More


Experts Talk at Mentor Booth

Experts Talk at Mentor Booth
by Pawan Fangaria on 05-11-2015 at 7:00 pm

It’s less than four weeks to go at DAC 2015 and the program is final now. So I started investigating new technologies, trends, methodologies, and tools that will be unveiled and discussed in this DAC. In the hindsight of the semiconductor industry over the last year, I see 14nm technologies in the realization stage and 10nm beckoning… Read More