DesignDash: ML-Driven Big Data Analytics Technology for Smarter SoC Design

DesignDash: ML-Driven Big Data Analytics Technology for Smarter SoC Design
by Kalar Rajendiran on 06-06-2022 at 10:00 am

DesignDash Better Decisions Faster

With time-to-market pressures ever increasing, companies are continually seeking enhanced designer productivity, faster design closure and improved project management efficiency. To accomplish these, organizations invest a lot in implementing both standardized approaches and proprietary techniques. With ever increasing… Read More


ISC 2022

ISC 2022
by Admin on 05-29-2022 at 12:00 am

SC 2022 – #TRANSFORMINGTHEFUTURE

THE EVENT FOR HIGH PERFORMANCE COMPUTING, MACHINE LEARNING AND DATA ANALYTICS

ISC HIGH PERFORMANCE 2022 PROGRAM

ISC High Performance is focused on bringing the most critical developments and trends in HPC, machine learning, and high performance data analytics to conference attendees.… Read More


Optimizing SoC performance in-life with Embedded Analytics

Optimizing SoC performance in-life with Embedded Analytics
by Admin on 05-12-2021 at 12:00 am

In many aspects of our lives, increasingly intelligent subsystems will do the thinking for us. 5G networks will self-tune to maximize their data throughput. Automation, with the help of AI, robotics, and the internet of things, is playing an increasing role in manufacturing. Vehicles are becoming ever more intelligent and autonomous.

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Gartner Data & Analytics Summit

Gartner Data & Analytics Summit
by Admin on 05-04-2021 at 12:00 am

May 4 – 6, 2021 | Americas | Virtual

Faced with a constantly evolving business landscape and unprecedented levels of uncertainty, it’s more vital than ever that data and analytics leaders such as the chief data officer and chief analytics officer (CDO and CAO) forge new paths to enable a data-and-analytics-centric culture within
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Optimization and verification wins in IoT designs

Optimization and verification wins in IoT designs
by Don Dingee on 08-17-2016 at 4:00 pm

Designers tend to put tons of energy into pre-silicon verification of SoCs, with millions of dollars on the line if a piece of silicon fails due to a design flaw. Are programmable logic designers, particularly those working with an SoC such as the Xilinx Zynq, flirting with danger by not putting enough effort into verification?… Read More


Lethal data injection a much bigger threat

Lethal data injection a much bigger threat
by Don Dingee on 08-08-2016 at 4:00 pm

Watching a spirited debate on Twitter this morning between Tom Peters and some of his followers reminded me of the plot of many spy movies: silently killing an opponent with a lethal injection of some exotic, undetectable poison. We are building in enormous risks in more and more big data systems.… Read More


TMR approaches should vary by FPGA type

TMR approaches should vary by FPGA type
by Don Dingee on 06-20-2016 at 4:00 pm

We’ve introduced the concepts behind triple modular redundancy (TMR) before, using built-in capability in Synopsys Synplify Premier to synthesize TMR circuitry into FPGAs automatically. A recent white paper authored by Angela Sutton revisits the subject… Read More


Should there be a 5-second IoT chip rule?

Should there be a 5-second IoT chip rule?
by Don Dingee on 01-12-2016 at 12:00 pm

Kids have a tendency to put things in their mouths. Any parent can relate to the statement, “Put that down! You don’t know where it’s been!” After the first child, concern usually relaxes quite a bit. People joke about a 5-second rule on the premise if an object was just dropped on the floor, it may not be contaminated yet.… Read More


A moment of IoT silence before we disrupt

A moment of IoT silence before we disrupt
by Don Dingee on 11-08-2015 at 12:00 pm

As I sat down in the SEMI Arizona Chapter breakfast meeting a few weeks ago, a moment of semiconductor history flew right before my eyes before the IoT sessions started.

We were seated in the cafeteria of Freescale Building 94 on Elliot Road in Tempe, a place I’d been many times before, except this time may have been the last. NXP is consolidating… Read More


Pushing on AXI-connected IP in FPGAs

Pushing on AXI-connected IP in FPGAs
by Don Dingee on 11-03-2015 at 12:00 pm

Success stories are great. Reading how someone uses a product contributes much more insight than reading about a product. Last month we had a teaser for a presentation by Wave Semiconductor; this month, we have the slides showing how they are using FPGA-based prototyping, AXI transactions, and DPI to speed up development.

First,… Read More