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Aldec reprograms HES7 for AXI4 speed

Aldec reprograms HES7 for AXI4 speed
by Don Dingee on 02-26-2016 at 4:00 pm

FPGA-based prototyping firms are all grappling with the problem of higher speed connectivity between a development host and their hardware. Aldec is announcing their solution at DVCon 2016, turning to an AMBA AXI4 interface bridged into a host with PCIe x8.

Faster host interfaces deliver dual benefits in FPGA-based prototyping. First is the FPGA configuration itself – to program a huge Xilinx FPGA (or more than one) means shipping a large file from the host down to the prototyping hardware. Second is at run time, where co-simulation runs on the host using transactors to control hardware execution in FPGAs. This hybrid solution allows users to run familiar visualization tools at much greater speeds than possible with host-based simulation alone, enabling more extensive verification testing.

What bus should be used to do that? In the not-too-distant past, people were turning to proprietary interfaces to the FPGA-based prototyping system, but those days are over. PCIe is ubiquitous in modern PC platforms and offers plenty of throughput in wider link widths. PCIe IP now widely available in FPGA form thanks to efforts from Xilinx, PLDA, CAST, and others. In some cases, where the SoC design is intended to run on PCIe, that interface might be carried through directly into the FPGAs on the prototyping platform.

A broader range of SoC designs does not contain PCIe at all. Most IP for ASICs today uses the AMBA AXI interconnect, not only for ARM cores but for other core architectures and peripherals. For those reasons much of the FPGA world has also turned to AXI. Xilinx has put extensive efforts into AXI4, taking advantage of its higher performance streaming and memory mapping capability. One IP protocol in the FPGA-based prototyping platform eases the learning curve, makes integration much easier, and offers the throughput and control features necessary for interaction with the host-based simulation package.

When Aldec said they used a non-proprietary backplane connector on their HES7XV4000BP, they meant it. Each of these edge connector slot cards carries one Xilinx Kintex-7 FPGA in a pre-defined configuration for host interfacing, and two Xilinx Virtex-7 FPGAs in user-defined configurations for the design under test. We haven’t seen the actual demo that Aldec will be showing at DVCon, but we have seen the documentation for the HES7ProtoAXI solution.

Without changing the hardware – after all, it is three FPGAs and can be reprogrammed – Aldec is launching a new software lob they refer to as HES7.ASIC.Proto2016.01 to create standard interfacing. The host interface to the Kintex-7 FPGA is now PCIe x8 (on that non-proprietary connector), offering transfer rates of 2GB/s into the card. Interfacing from the Kintex-7 to the two Virtex-7 FPGAs, and the connection between those two parts, is now AXI4.

It’s fast in terms of hardware bandwidth. The AXI4 connections into the DUT logic are 256 bits wide running at 125 MHz. Aldec has also taken care of all the address remapping for transactions, using that DDR3 memory DIMM on the board. The rest is business as usual – there is a C++ API that the testbench on the host uses to create read and write transactions, now in theory running much faster over the PCIe x8 and AXI4 interfaces.

I expect Aldec will show just how much faster this is for co-simulation in their demonstration. If you’re at DVCon at the DoubleTree in San Jose next week, drop by the Aldec booth #602 and see this solution. For more on the concept including the Getting Started guide (one-time registration for download), visit the Aldec site:

Aldec to unveil HES-7 High-speed AXI Transmission Channel at DVCon 2016

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