With growing size and complexity of SoC, the semiconductor community is realizing the growing pain of verification. The cost of SoC verification grows exponentially with design size. Moreover, there is no single methodology for verifying a SoC; multiple engines are used in different contexts through different verification flows. Also, design verification methodology changes from low level design up to the system level. This keeps multiple teams engaged in doing more or less similar things in different contexts, being in silos without any effective communication between them.
It’s apparent that a significant portion of verification cost is due to duplication of efforts between different test methodologies. Currently, software driven verification methodology is being looked at as the top-down approach which could prove worthy to abstract tests at system level and map them to different verification platforms through portable code. This approach can provide a large productivity through reuse of tests, provided they can be shared across multiple platforms in standard formats.
Wait, it’s not only about test duplication. When we talk about software driven verification methodology, we must check deeper into lower levels to understand what drives hardware-software interfaces. Today, there are multiple versions of software in use for system modelling, RTL verification, bare-metal driver for SoC bring-up, and OS driver. These different versions of driver software are being created by different teams (in different geographies and even different organizations) in different languages for almost same functionality under different operating environments. There is a lot of duplication of effort here in software development too. Note that the lack of a common formal specfor the hardware-software interface (ideally to be shared by different teams) adds to the problem.
Recently, Accelleraannounced the formation of Portable Stimulus Working Group (PSWG) with participation from the leaders in EDA and semiconductor industry. The charter of this group is to develop a Portable Test and Stimulus Standard for defining a common specification across all levels under different configurations that can be shared across the industry between different verification platforms.
It’s interesting to learn about a variety of companies (in semiconductor and electronics world) joining hands together to realize the PSWG strategy on a larger scale. Vayavya Labs, a company delivering embedded system design tools and solutions for last several years has joined the PSWG initiative to deliver a common standard for Hardware/Software Interface (HSI) specification.
Vayavya has immense expertise in device driver and firmware development, hardware board bring-up, OS porting, hardware modelling & prototyping. Driven by this expertise, Vayavya counts several Semiconductor, IP and EDA companies as its customers for hardware-software co-verification, embedded software development, system design, and so on.
Vayavya Labsis headquartered in India with its subsidiary, Vayavya Labs Inc. in USA. Their technology is based on important patents filed by them in USPTO. I will talk more about Vayavya later. For now, let’s review what Vayavya is delivering to PSWG and how it will benefit the overall semiconductor industry.
Vayavya proposes a standard specification language to capture hardware-software interface. Vayavya’s contribution in PSWG is derived from their own language called DPS for specifying Hardware/Software Interface. The Device Programming Sequence (DPS) captures device programming aspects such as register meta-data and access, device capabilities and configurations, FIFO management, descriptor management, interrupt management, programming sequences, and so on. It is worth emphasizing again that DPS is much more than just a simple register specification.
The Runtime Specification (RTS) captures details of the operating environment. The DPS and RTS for a particular device driver are fed to an automated tool that generates the device driver for the target operating environment.
To put the things in perspective, this methodology allows hardware and software teams to focus on writing the DPS and RTS specifications only and not duplicate the effort in writing multiple device drivers in their entirety. Clearly, this methodology saves a significant amount of time, effort, and cost of SoC verification, specifically at hardware-software interface level.
Connecting the dots together with the overall software driven verification methodology, the environment specific tests are derived from Scenario Specification of applications running on a system. The drivers are generated from the DPS (i.e. HSI Specification) for different target operating environments. The environment specific tests and drivers are compiled together to form the executables for particular platforms. This is the most simplistic representation; there are multiple processing steps involved at each stage in this.
This level of contribution by Vayavya in solving such complex issues in SoC verification space will go a long way in the semiconductor industry. Going forward, we are expected see more products, technologies and solutions from Vayavya.
Karthick Gururaj, Principal Architect at Vayavya Labs is one of the panellists in a panel on Portable Stimulus at DVCon USA –
March 02, 12:00PM – 1:15PM – Software Driven Verification with Portable Stimulus: The Next Productivity Leap Enabling the Continuum of Verification Engines
To know more about this panel and attend, click HERE.