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Design Verification Challenges: Past, Present and Future!

Design Verification Challenges: Past, Present and Future!
by Daniel Nenni on 02-26-2016 at 7:00 am

 Next week I will be at DVCON which is not to be confused with DEFCON the community of black and white hat hackers that challenge our online privacy on a daily basis. DVCON is the premier conference for the functional design and verification of our beloved electronic devices. The big draw next week of course is the keynote by Dr. Walden Rhines:

Design Verification Challenges: Past, Present and Future
Every time design verification methodologies standardize enough to become manageable, a new set of requirements emerges. Dr. Rhines will review the history of each major phase of verification evolution and then concentrate on the challenges of newly emerging problems. While functional verification still dominates the effort, new requirements for security and safety are becoming more important and will ultimately involve challenges that could be more difficult than those we have faced in the past.

Wally is a semiconductor and EDA historian and he knows verification, absolutely. Wally also helped fact check both of our books (Fabless: The Transformation of the Semiconductor Industry and Mobil Unleashed) and his keynotes are legendary so you are not going to want to miss this. I hope to get his slides and talk to him at the conference so I will write more after that. Here are the other DEVCON Mentor events that you should also not miss:

Featured Tutorials
Cut Your Design Time in Half with Higher Abstraction
When: Monday, Feb. 29[SUP]th[/SUP], 2:00pm – 5:00pm
Where: Oak
Presenters: Bob Condon (Intel), Frederic Doucet (Qualcomm), Peter Frey (Mentor), Mike Meredith (Cadence), Dirk Seynhaeve (Intel)
Link: https://dvcon.org/content/event-details?id=199-3-T

Advanced Validation and Functional Verification Techniques for Complex Low Power SoCs [Mentor Sponsored Tutorial]
When: Thursday, March 3[SUP]rd[/SUP], 8:30am – Noon
Where: Donner
Presenters: Gabriel Chidolue (Mentor), Shantanu Samant (Mentor), Desinghu PS (ARM)
Link: https://dvcon.org/content/event-details?id=199-5-T

Back to Basics: Doing Formal the Right Way [Mentor Sponsored Tutorial]
When: Thursday, March 3[SUP]rd[/SUP], 2:00pm – 5:30pm
Where: Donner
Presenters: Joe Hupcey (Mentor), Mark Eslinger (Mentor), Doug Smith (Mentor)
Link: https://dvcon.org/content/event-details?id=199-9-T

Tuesday – Mentor Sponsored Luncheon: Enterprise Verification – Visualize This!
When: Tuesday, March 1[SUP]st[/SUP], 12:00pm – 1:15pm
Where: Pine/Cedar
Presenters: Steve Bailey (Mentor)
Link: https://dvcon.org/content/event-details?id=199-131

Paper/Oral Presentations (Regular Sessions)
Tuesday, March 1[SUP]st[/SUP] | Session 3: Low Power Verification |9:00am – 10:30am | Monterey/Carmel
3.2 UPF Generic References: Unleashing the Full Potential
Speaker: Jitesh Bansal – Mentor Graphics Corp.

Tuesday, March 1[SUP]st[/SUP] | Session 7: Effective Emulation | 3:00pm – 4:30 | Monterey/Carmel
7.2 Activity Trend Guided Efficient Approach for Peak Power Estimation Using Emulation Speaker: Saurabh Jain – Mentor Graphics Corp.

Wednesday, March 2[SUP]nd[/SUP] | Session 8: UVM Applications – II | 10:00am – 12:00pm | Oak
7.2 Parameters, UVM, Coverage & Emulation – Take Two and Call Me In the Morning
Speaker: Michael Horn – Mentor Graphics Corp.

Wednesday, March 2[SUP]nd[/SUP] | Session 10: Verification Processes and Resource Management | 10:00am – 12:00pm | Monterey/Carmel
10.1 Verification Patterns – Taking Reuse to the Next Level
Speaker: Harry Foster – Mentor Graphics Corp.

Wednesday, March 2[SUP]nd[/SUP] | Session 11: UVM Applications – III | 3:00pm – 4:30pm | Oak
11.2 No RTL Yet? No Problem – UVM Testing a SystemVerilog Fabric Model
Speaker: Rich Edelman – Mentor Graphics Corp.

Poster Session
When: Tuesday, March 1[SUP]st[/SUP] 10:00am – 12:30pm
Where: Gateway Foyer (2[SUP]nd[/SUP] Floor)

Featured Posters:
4P.8 Cross Coverage of Power States
Speaker: Veeresh Singh – Mentor Graphics Corp.

4P.18 Introspection into SystemVerilog Without Turning it Inside Out
Speaker: Dave Rich – Mentor Graphics Corp.

4P.19 Power State to PST Conversion: Simplifying Static Analysis and Debugging of Power Aware Designs
Speaker: Madhur Bhargava – Mentor Graphics Corp.

4P.21 Reset and Initialization, the Good, the Bad and the Ugly
Speaker: Ping Yeung – Mentor Graphics Corp.

4P.24 Evolution of TRIAGE – Realtime Improvements in Debug Productivity
Speaker: Gordon Allan – Mentor Graphics Corp.

4P.26 Verification with Multi-Core Parallel Simulations: Have You Found Your Sweet Spot Yet?
Speaker: Rohit Jain – Mentor Graphics Corp.

4P.38 Jump-Start Portable Stimulus Test Creation with SystemVerilog Reuse
Speaker: Matthew Ballance

4P.40 A New Class of Registers
Speaker: Mark Peryer – Mentor Graphics Corp.

4P.35 Slaying the UVM Reuse Dragon. Issues and Strategies for Achieving UVM Reuse
Speakers: Bob Oden – Mentor Graphics Corp. / Michael Baird – Willamette HDL