Verification Completion: When is enough enough?  Part I

Verification Completion: When is enough enough?  Part I
by Dusica Glisic on 09-30-2021 at 6:00 am

Tunnel min

Verification is a complex task that takes the majority of time and effort in chip design. Veriest shares customer views on what this means. We are an ASIC services company, and we have the opportunity to work on multiple projects and methodologies, interfacing with different experts.

In this “Verification Talks”… Read More


Podcast EP5: Verification, Evolution and Revolution

Podcast EP5: Verification, Evolution and Revolution
by Daniel Nenni on 01-29-2021 at 10:00 am

Dan and Mike are joined by Dr. Bernard Murphy. Bernard has recently published a book on entrepreneurship and the importance of storytelling. In this podcast, Bernard talks about his journey from a PhD in Nuclear Physics at Oxford University to a storied career in EDA and verification. Bernard discusses a fundamental shift in… Read More


Dr. Walden Rhines on the Past Present and Future!

Dr. Walden Rhines on the Past Present and Future!
by Daniel Nenni on 03-06-2016 at 7:00 am

Who can present seventy six slides in sixty minutes, still have time for questions, AND make it interesting? Dr. Walden Rhines that’s who. Here is a link to the presentation but I have to warn you, it is a 100MB PDF file:

Design Verification Challenges: Past, Present, and Future

The DVCon conference was well attended again this year… Read More


Design Verification Challenges: Past, Present and Future!

Design Verification Challenges: Past, Present and Future!
by Daniel Nenni on 02-26-2016 at 7:00 am

Next week I will be at DVCON which is not to be confused with DEFCON the community of black and white hat hackers that challenge our online privacy on a daily basis. DVCON is the premier conference for the functional design and verification of our beloved electronic devices. The big draw next week of course is the keynote by Dr. Walden… Read More