Ajoy – History, Perspectives and Crossing the Chasm

Ajoy – History, Perspectives and Crossing the Chasm
by Bernard Murphy on 03-06-2016 at 4:00 pm

EDAC hosted an event at DVCon this week where Jim Hogan interviewed Ajoy Bose (CEO of Atrenta prior Image Removedto its acquisition by Synopsys). The nominal purpose was to talk about turning a venture into a valuable enterprise. This was covered but, in Jim’s way, it was really a more wide-ranging and personal interview. This is… Read More


Dr. Walden Rhines on the Past Present and Future!

Dr. Walden Rhines on the Past Present and Future!
by Daniel Nenni on 03-06-2016 at 7:00 am

Image RemovedWho can present seventy six slides in sixty minutes, still have time for questions, AND make it interesting? Dr. Walden Rhines that’s who. Here is a link to the presentation but I have to warn you, it is a 100MB PDF file:

Design Verification Challenges: Past, Present, and Future

The DVCon conference was well attended… Read More


Solving the Next Big SoC Challenges with FPGA Prototyping

Solving the Next Big SoC Challenges with FPGA Prototyping
by Daniel Nenni on 03-01-2016 at 4:00 pm

The health of the semiconductor industry revolves around the “start”. Chip design starts translate to wafer starts, and both support customer design wins and product shipments. Roadmaps develop for expanding product offerings, and capital expenditures flow in to add capacity enabling more chip designs and wafer starts. If… Read More


Design Verification Challenges: Past, Present and Future!

Design Verification Challenges: Past, Present and Future!
by Daniel Nenni on 02-26-2016 at 7:00 am

Image RemovedNext week I will be at DVCON which is not to be confused with DEFCON the community of black and white hat hackers that challenge our online privacy on a daily basis. DVCON is the premier conference for the functional design and verification of our beloved electronic devices. The big draw next week of course is the keynote… Read More