Register Management is the Foundation of Every Chip

Register Management is the Foundation of Every Chip
by Mike Gianfagna on 11-17-2021 at 6:00 am

Register Management is the Foundation of Every Chip

Virtually every chip today runs software. And that software needs to interact with and control the hardware on the chip. There are typically many interfaces to manage as well as dedicated hardware accelerators to coordinate. In fact, many of those hardware accelerators are present only to support the execution of the software… Read More


Reusable HW/SW Interface for Portable Stimulus

Reusable HW/SW Interface for Portable Stimulus
by Pawan Fangaria on 06-03-2016 at 7:00 am

Although semiconductor community has ushered into the era of SoCs, the verification of SoCs is still broken. There is no single methodology or engine to verify a complete SoC; this results in duplication of efforts and resources for test creation and verification at multiple stages in the SoC development, albeit with different… Read More


CEO Insight: Transformation of Vayavya Labs into System Design Automation

CEO Insight: Transformation of Vayavya Labs into System Design Automation
by Pawan Fangaria on 05-12-2016 at 7:00 am

With the advent of SoCs, design abstractions and verification has moved up at the system level. It’s imperative that EDA moves up the value chain to start design automation at system level. The System Design Automation will be the new face of EDA in coming years.… Read More


HW/SW Interfaces for Portable Stimulus

HW/SW Interfaces for Portable Stimulus
by Pawan Fangaria on 02-26-2016 at 12:00 pm

With growing size and complexity of SoC, the semiconductor community is realizing the growing pain of verification. The cost of SoC verification grows exponentially with design size. Moreover, there is no single methodology for verifying a SoC; multiple engines are used in different contexts through different verification… Read More