Virtually every chip today runs software. And that software needs to interact with and control the hardware on the chip. There are typically many interfaces to manage as well as dedicated hardware accelerators to coordinate. In fact, many of those hardware accelerators are present only to support the execution of the software in a specific way. Most AI algorithms work like this. If you’re a software engineer, you will recognize the need for device drivers to accomplish these tasks. If you’re an architect, you know the register map is what makes the device drivers work. Managing those registers is a complex task and Semifore has a great white paper that explains the moving parts of this process. Read on to see why register management is the foundation of every chip.
The register map implements something often called the hardware/software interface, or HSI. It’s the critical part of the design that ensures the device drivers can do what they’re supposed to. Getting the details of this part of the design correct, at the beginning is an important part of a successful project. It doesn’t end there, however. A complex HSI can have millions of 64-bit registers. During design, bits in those registers can change quite often, many times per day. That necessitates creating a new version of the HSI and all the supporting documentation that often as well. A methodology with substantial automation is the only way forward in this situation.
Where Semifore Fits
Semifore focuses exclusively on addressing the development of a verified, correct-by-construction HSI and propagating all the required formats to the various members of the design team. Ensuring everyone on the team is using consistent, up-to-date information is a critical item for smooth execution. Team members that need a unique format describing the HSI include RTL designers, verification engineers, software engineers and documentation staff. You can learn more about Semifore in this interview with Rich Weber, Semifore’s co-founder and CEO.
The White Paper
The Semifore white paper provides a great overview of the challenges of building the HSI and details that methodology with substantial automation I previously mentioned. The benefits of such a methodology are outlined in the white paper, as well as the pitfalls of trying to do it yourself.
A product design cycle is detailed to help you understand how the methodology fits. Aspects covered include:
- Product definition phase
- Product implementation phase
- RTL verification
- Software development
Each section includes a detailed look at best practices and the benefits of following those practices. This document summarizes many years of experience Semifore has logged helping customers design highly complex chips. Reading it will save you a lot of time. You can access the white paper here.
One of the very challenging aspects of the HSI is managing all the objects and parameters that define its structure and behavior. There are industry standards that address part of this problem. There are also aspects not covered by those standards. It turns out Semifore has a solution for this problem as well. They have developed a language that is part of its product offering that picks up where the standards leave off.
It’s a way to build a real executable specification of your design. As a bonus, here is a link to the document that explains all the formats that need to be tracked, and how to capture them. After reading these white papers, you will appreciate why register management is the foundation of every chip, and how to build a solid foundation.
Webinar: Semifore Offers Three Perspectives on System Design Challenges
CEO Interview: Rich Weber of Semifore, Inc.Share this post via:
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