A Solid Methodology is the Margin of Victory

A Solid Methodology is the Margin of Victory
by Mike Gianfagna on 08-02-2022 at 6:00 am

A Solid Methodology is the Margin of Victory

Designing complex systems is difficult. It seems to me that the difficulty has increased at a rate that is more exponential than linear with design complexity. Some version of Moore’s law for design is at work. The challenges for advanced designs just seem to keep mounting. A new item that is top of mind for many executives is the talent… Read More


The Silent Revolution is Underway, and Semifore is at its Epicenter

The Silent Revolution is Underway, and Semifore is at its Epicenter
by Mike Gianfagna on 07-21-2022 at 10:00 am

The Silent Revolution is Underway and Semifore is at its Epicenter

There is a major shift in innovation occurring all around us. We see the results every day.  We can interact with them in an easier, more intuitive way. They deliver insights about our health and our daily habits. All this can be categorized as a move towards Smart Everything – ubiquitous machine-assisted intelligence for the good… Read More


Webinar: Semifore Offers Three Perspectives on System Design Challenges

Webinar: Semifore Offers Three Perspectives on System Design Challenges
by Mike Gianfagna on 02-14-2022 at 10:00 am

Three Perspectives on the HardwareSoftware Interface – Whos Right

The exponential increase in design complexity is a popular topic these days. In fact, it’s been a topic of discussion for a very long time. The explosion of chip and system design complexity over the past ten years has become legendary and haunts many of us daily. A lot of the complexity we face has to do with coordinating across an ever-increasing… Read More


Register Management is the Foundation of Every Chip

Register Management is the Foundation of Every Chip
by Mike Gianfagna on 11-17-2021 at 6:00 am

Register Management is the Foundation of Every Chip

Virtually every chip today runs software. And that software needs to interact with and control the hardware on the chip. There are typically many interfaces to manage as well as dedicated hardware accelerators to coordinate. In fact, many of those hardware accelerators are present only to support the execution of the software… Read More


Reusable HW/SW Interface for Portable Stimulus

Reusable HW/SW Interface for Portable Stimulus
by Pawan Fangaria on 06-03-2016 at 7:00 am

Although semiconductor community has ushered into the era of SoCs, the verification of SoCs is still broken. There is no single methodology or engine to verify a complete SoC; this results in duplication of efforts and resources for test creation and verification at multiple stages in the SoC development, albeit with different… Read More