Reusable HW/SW Interface for Portable Stimulus

Reusable HW/SW Interface for Portable Stimulus
by Pawan Fangaria on 06-03-2016 at 7:00 am

Although semiconductor community has ushered into the era of SoCs, the verification of SoCs is still broken. There is no single methodology or engine to verify a complete SoC; this results in duplication of efforts and resources for test creation and verification at multiple stages in the SoC development, albeit with different verification engines. Considering the breadth and depth of verification required for an SoC, there does not seem any other alternative than going through the rigorous process of verifying the SoC with multiple engines in different situations.

Does that leave us spending exponentially in testing and verification of ever growing SoCs forever? It’s time we find innovative ways to curtail duplication at various levels of testing activities. What if the test-case generation is automated and reused across various SoC stages and verification engines? We would need automated and reusable hardware-software interfaces for actual execution of those test-cases too. So, where do we stand? The good news is that things in this direction are progressing more rapidly than I could anticipate.

One of the goals of Accellera’s Portable Stimulus initiative is deploying software driven verification by enabling specification of test scenarios that are verification platform agnostic. The generation of test-cases from different scenarios can be automated and mapped to different verification platforms. This methodology seems promising for reuse of test scenarios at block, IP, and SoC level as well.

A key consideration and complexity in the software driven verification methodology comes when a driver has to be implemented for actual execution of a test on a desired verification platform. This part of the hardware-software interface (HSI) development has remained largely manual. One can imagine the amount of resources, time, and effort being spent in this activity, duplicated for every environment as shown in the figure below:


Vayavya Labshas proposed a novel methodology for automating the driver development. This methodology revolves around capturing the hardware-software interface specificationsand run-time specifications in standard formats and generating the drivers for multiple operating environments through automated tools. Automatic driver generation meets a critical need in ensuring the generated test cases run on different verification platforms seamlessly.

Vayavya’s HSI technology is already in use in the electronic and the semiconductor verification industry. Customers have adopted Vayavya’s methodology in their flow where they transform their device specifications to Vayavya’s standard DPS (Device Programming Sequence) format. And by specifying run-time environment in a standard RTS (Runtime Specification) format and using Vayavya’s DDGen (a versatile tool for device driver generation) they can generate drivers for any operating environment such as SystemVerilog driver for verification, BareMetal C driver for validation, and SystemC driver for virtual platform. The generated SystemVerilog drivers are interoperable with UVM (Universal Verification Methodology). Customers treat the HSI specification as a golden specification without leaving any ambiguity in communication between various stakeholders in the team including architects, designers, verification and validation engineers, software engineers and so on.

Also, the HSI methodology is being adopted in larger semiconductor ecosystem of software driven verification tools. While a standard representation enables specification of reusable test scenarios, HSI would additionally enable specification of reusable drivers, thus ensuring the execution of test on any desired verification platform. Vayavya is an active contributing member and is leading standardization of HSI in Portable Stimulus Working Group (PSWG) setup by Accellera.

Cadenceis a leading player in the semiconductor EDA industry for software driven verification tools and methodology at system level. Perspec[SUP]TM[/SUP]System Verifier is a major contribution from Cadence for software driven verification. It provides a complete environment for generating system level test-cases from use-case specification.


In the Perspec flow, actions of design components typically consist of an “exec body” that makes calls to driver APIs for test execution. Before Vayavya’s technology, users had to separately provide the driver implementation for different verification platforms. Vayavya introduced DDGen which takes programmer’s view of the device as input in DPS format and a few lines of code to define run-time environment in RTS format, and automatically generates drivers for different platforms.

One can imagine how this level of automation for test-case generation and execution on multiple verification and validation platforms can enhance verification productivity by an order of magnitude. The DDGen integration with Perspec makes it easy and efficient to deploy for system level verification of SoCs. The Perspec – DDGen integrated solution for system level test-case generation and execution has been verified in a post-silicon environment on Zedboard consisting of Xilinx Zynq 7000 SoC.

The Perspec – DDGen integration will be presented by Vayavya at 53[SUP]rd[/SUP] DAC in Cadence Theatre. Attend the following session to know more about Perspec System Verifier, DDGen and the new methodology for software driven verification –

Date/Time: 7[SUP]th[/SUP] June 2016, 2 PM
Venue: Cadence Theatre in 53[SUP]rd[/SUP] DAC at Austin, TX
Topic: Software-Driven Validation: Using Perspec System Verifier and DDGen

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