IMEC is a technology research center located in Belgium that is one of the premier semiconductor research centers in the world today. The IMEC Technology Forum (ITF) is a two-day event attended by approximately 1,000 people to showcase the work done by IMEC and their partners.
Gary Patton is the Chief Technical Officer and Senior Vice President of Worldwide R&D at Global Foundries. Gary was part of a panel discussion during the “Scaling is dead. Long live scaling” session, he then delivered a keynote presentation entitled Moving the Electronics Industry Forward: Technology Enablers for the Next Wave of Growth and finally I had the opportunity to interview him. In this blog I will discuss Gary’s presentation and my follow up interview. I will blog about the panel discussion separately. I will start with Gary’s keynote and then discuss our interview which gave me an opportunity to follow up on some of the points from his talk and also touch base on Global Foundries progress since I last interviewed him in November 2015.
My blog on our November 2015 interview is available here.
Technology Enablers paper:
Traditional growth drivers are flat, PCs are down and mobile growth has slowed. The semiconductor industry has gone through many transitions in the past. Corporate computing, military and telecommunications drove the industry from 1965 to 1985, from 1985 to 1995 it was the PC/smart client, from 1995 to 2005 we saw internet, gaming consoles and e-commerce, and from 2005 to 2015 we saw mobile as a driver. What will be the next driver? We have also seen technology transitions from bipolar to CMOS, the introduction of high-k metal gates (HKMG) and strain and then FinFETs have carried us for a few years and will carry us for a few more years.
He thinks 5G will be as disruptive to mobile as data was. Mobile with 5G allows massive connectivity and video download and upload. Internet Of Things (IOT) wearables nearly doubled this year, it will fuel connectivity and 5G. Autonomous cars are coming, there is $350 of semiconductors in a car today, that will grow substantially. Autonomous cars can reduce the number of required cars and urban parking lots. IOT is projected to be $50 to $75 billion dollars in the 2019-2020 time frames. All of those devices will generate data that has to go into the cloud. Data volumes are increasing 25% per year and data centers double every three years.
There is a need for innovation. It used to be that when you scaled down you got cost, performance and power but today you don’t get all that. You can still drive down cost but it is getting exponentially more expensive to develop. Most key technologies were in development for at least ten years. FinFET electrostatics are limited and will likely transition to nanowires and vertical FETs with FDSOI as an option for low power applications. Highly integrated optics will be needed for shorter copper lines.
The transition to fully depleted FinFETs gave us lots of drive current for large chips, FDSOI is an option for low power. We need to optimize the power/cost trade off. A 14nm FinFET design is 2.5x the cost of a 28nm planar design. FDSOI gives a lower cost design option that you can forward bias for performance or reverse bias for power. You can dynamically control the bias with software and FDSOI provides easy integration of analog and RF.
Photonics has moved from 180nm with integrated photonics to 90nm this year and 65nm interposers with integrated photonics are in the works.
EUV will be in manufacturing by 2020 or sooner. Better power (200 watts has been shown), better photoresist sensitivity and pellicles, Gary expects 7nm to be a long lived node and EUV will be inserted when ready. I will discuss this more in the blog on the panel discussion but Gary noted that we may not take full advantage of the technology at least initially. Inserting EUV can reduce 30 masks to 10 masks and at 1.5 days per mask layer save 30 days of cycle time.
He thinks packaging is a big opportunity. Over the time that silicon has improved by 1000x package sizes have been reduced by 3x.
Collaboration will be key, Global Foundries is engaged with CNSE, IMEC, IBM, EDA and Universities. They have FDSOI, MRAM, RF-SOI and SiGe, FinFETs, Advanced Packaging and ASICs. They also have 5 manufacturing centers on 3 continents.
Later the same day I got to sit down with Gary for a follow-up interview.
As we discussed at our previous meeting in November 2015, Gary discussed that execution had been an issue in the past and they are really pushing hard on that. They have implemented a technology council to break down barriers, they also do milestone reviews where they bring in experts from around the company to do technology deep dives and that is really paying off. 22 FDSOI has hit all of its milestones and is ahead on yield. Full production is expected in 2017 with risk production at the end of 2016. 14nm is also hitting all of its milestones, yields are good and there are a ton of tape-outs. 14nm went into production earlier this year.
They are working on 10nm but focused on 7nm. They haven’t announced whether they will do 10nm. He did mention that some customers have told them they will skip 10nm for 7nm. My understanding is that 10nm is a kind of intermediate node mostly targeted at Cell Phones Applications Processors. That isn’t a big segment for Global Foundries so personally I wouldn’t be surprised if they skipped 10nm and went right to 7nm, but Gary wouldn’t comment on this yet.
One comment I found really interesting is they are using EUV for non-transistor layers to save development time by avoiding all the processing for multi-patterning. Cycle time is coming up a lot in discussions lately because of all of the process complexity we are seeing. He also noted that the bar is getting lower for EUV because you can take out so many multi-patterning cut/block masks with a single EUV exposure. He thinks EUV will be used at contact and via first and for block masks on metal layers. They are currently doing an 80 watt upgrade on the Albany EUV tool.
The RF business is doing well and they are putting a lot of money into it. Gary just sent one of his best RF experts to Dresden to support RF on the 22FDx process. RF is very hard to do with FinFET because you can only add fins in discrete increments. They are working on a next generation FDSOI technology but haven’t put a number on it. He thinks 22nm FDSOI design costs are similar to 28nm design costs (versus 2.5x for 14nm FinFETs as mentioned above). FDSOI has lower capacitance than FinFETs and small IOT chips are capacitance dominated. They are getting a lot of interest. They are building up IP working with Invecas and ARM is really starting to focus on FDSOI.
Their ASIC business is leveraging their 14LLP process and getting a lot of traction. 5G will touch many sites and will use a wide range of technologies, including 7nm.
Global Foundries will do FinFETs for 7nm but he doesn’t think you can do FinFETs beyond 7nm. He thinks horizontal nanowires are next. There may be a “shrink” of 7nm FinFETs but the dimensions won’t shrink much, it may just be implementing EUV.Share this post via: