VLSI Symposium 2020 – Imec Monolithic CFET

VLSI Symposium 2020 – Imec Monolithic CFET
by Scotten Jones on 09-13-2020 at 10:00 am

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The 2020 VLSI Technology Symposium was held as a virtual conference from June 14th through June 19th. At the symposium Imec gave an interesting paper on Monolithic CFET and I had a chance to interview one of the authors, Hiroaki Arimura.

It is well known in the industry that FinFETs (FF) are reaching the end of their scaling life. Samsung… Read More


SEMICON West – Applied Materials Selective Gap Fill Announcement

SEMICON West – Applied Materials Selective Gap Fill Announcement
by Scotten Jones on 08-17-2020 at 5:00 pm

Applied Materials Selective Gapfill July 2020 Page 02

At SEMICON West, Applied Materials announced a new selective gap fill tool to address the growing resistance issues in interconnect at small dimensions. I had the opportunity to discuss this new tool and the applications for it with Zhebo Chen global product manager in the Metal Deposition Products group at Applied Materials.… Read More


Imec Technology Forum and ASML

Imec Technology Forum and ASML
by Scotten Jones on 07-30-2020 at 6:00 am

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On Thursday July 9 Imec held a virtual technology forum. Imec is one of the premier research organizations working on semiconductor technology and their forums are always interesting. My area of interest is process technology and the following are my observation in that area from the forum.

Luc Van Den Hove
Luc Van Den Hove is the… Read More


VLSI Symposium 2020 – Imec Buried Power Rail

VLSI Symposium 2020 – Imec Buried Power Rail
by Scotten Jones on 07-26-2020 at 10:00 am

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The 2020 VLSI Technology Symposium was held as a virtual conference from June 14th through June 19th. At the symposium Imec gave an interesting paper on Buried Power Rails (BPR) and I had a chance to interview one of the authors, Anshul Gupta.

As logic devices continue to scale down metal pitch is reaching a limit. Imec defines a pitch… Read More


Key Semiconductor Conferences go Virtual

Key Semiconductor Conferences go Virtual
by Scotten Jones on 06-24-2020 at 2:00 pm

IEDM 2020 Logo

This last week the 2020 Symposia on VLSI Technology and Circuits (VLSI Conference) was held as a virtual conference for the first time and it was announced today (June 24th) that this year’s IEDM conference will also be held as a virtual conference.

“The IEDM Executive Committee has decided that in the interest of prioritizing the… Read More


Effect of Design on Transistor Density

Effect of Design on Transistor Density
by Scotten Jones on 05-26-2020 at 10:00 am

TSMC N7 Density Analysis SemiWiki

I have written a lot of articles looking at leading edge processes and comparing the process density. One comment I often get are that the process density numbers I present do not correlate with the actual transistor density on released products. A lot of people want to draw conclusions an Intel’s processes versus TSMC’s processes… Read More


Cost Analysis of the Proposed TSMC US Fab

Cost Analysis of the Proposed TSMC US Fab
by Scotten Jones on 05-19-2020 at 10:00 am

TSMC US Fab SemiWiki

On May 15th TSMC “announced its intention to build and operate an advanced semiconductor fab in the United States with the mutual understanding and commitment to support from the U.S. federal government and the State of Arizona.”

The fab will run TSMC’s 5nm technology and have a capacity of 20,000 wafers per month (wpm). Construction… Read More


Can TSMC Maintain Their Process Technology Lead

Can TSMC Maintain Their Process Technology Lead
by Scotten Jones on 04-29-2020 at 10:00 am

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Recently Seeking Alpha published an article “Taiwan Semiconductor Manufacturing Company Losing Its Process Leadership To Intel” and Dan Nenni (SemiWiki founder) asked me to take a look at the article and do my own analysis. This is a subject I have followed and published on for many years.

Before I dig into specific process density… Read More


SPIE 2020 – ASML EUV and Inspection Update

SPIE 2020 – ASML EUV and Inspection Update
by Scotten Jones on 04-20-2020 at 10:00 am

0.33 NA EUV systems for HVM Ron Schuurhuis Page 02

I couldn’t attend the SPIE Advanced Lithography Conference this year for personal reasons, but last week Mike Lercel of ASML was nice enough to walk me through the major ASML presentations from the conference.

Introduction
In late 2018, Samsung and TSMC introduced 7nm foundry logic processes with 5 to 7 EUV layers, throughout … Read More


SPIE 2020 – Applied Materials Material-Enabled Patterning

SPIE 2020 – Applied Materials Material-Enabled Patterning
by Scotten Jones on 03-13-2020 at 10:00 am

2020 SPIE Media Briefing Full Slides for Scott Jones Page 16

I wasn’t able to attend the SPIE Advanced Lithography Conference this year for personal reasons, but Applied Materials was kind enough to set up a phone briefing for me with Regina Freed to discuss their Materials-Enabled Patterning announcement.

At IEDM Applied Materials (AMAT) tried to put together a panel across the entire… Read More