Intel to present Intel 4 process at the VLSI Technology Symposium

Intel to present Intel 4 process at the VLSI Technology Symposium
by Scotten Jones on 05-20-2022 at 8:00 am

VLSI Symposium 2022 SemiWiki 1

The VLSI Symposium on Technology & Circuits will be held in Hawaii from June 12th to June 17th. You can register for the conference here.

The tip sheet for the conference has been released and one thing that caught my eye is some data from the Intel 4 paper that Intel will be presenting at the conference.

Intel’s old roadmap had 14nm,… Read More


The Lost Opportunity for 450mm

The Lost Opportunity for 450mm
by Scotten Jones on 04-15-2022 at 6:00 am

450mm Wafer SemiWiki


I spent several days this week at the SEMI International Strategy Symposium (ISS). One of the talks was “Can the Semiconductor Industry Reach $1T by 2030” given by Bob Johnson of Gartner. His conclusion was, that $1 trillion dollars is an aggressive forecast for 2030 but certainly we should reach $1 trillion dollars in the next 10… Read More


Intel and the EUV Shortage

Intel and the EUV Shortage
by Scotten Jones on 04-13-2022 at 10:00 am

Slide1

In my “The EUV Divide and Intel Foundry Services” article available here, I discussed the looming EUV shortage. Two days ago, Intel announced their first EUV tool installed at their new Fab 34 in Ireland is a tool they moved from Oregon. This is another indication of the scarcity of EUV tools.

I have been tracking EUV system production… Read More


Can Intel Catch TSMC in 2025?

Can Intel Catch TSMC in 2025?
by Scotten Jones on 04-11-2022 at 6:00 am

Slide6

At the ISS conference held from April 4th through 6th I presented on who I thought would have the leading logic technology in 2025. The following is a write up of that presentation.

ISS was a virtual conference in 2021 and I presented on who currently had logic leadership and declared TSMC the clear leader. Following that conference,… Read More


The EUV Divide and Intel Foundry Services

The EUV Divide and Intel Foundry Services
by Scotten Jones on 03-23-2022 at 10:00 am

Intel IDM 2.0 Process Roadmap
The EUV Divide

I was recently updating an analysis I did last year that looked at EUV system supply and demand, while doing this I started thinking about Intel and their Fab portfolio.

If you look at Intel’s history as a microprocessor manufacturer, they are typically ramping up their newest process node (n), in volume production… Read More


Intel 2022 Investor Meeting

Intel 2022 Investor Meeting
by Scotten Jones on 02-21-2022 at 6:00 am

Figure 1 Process Innovations

Last Thursday Intel held their investors meeting, in this write up I wanted to focus on my areas of coverage/expertise, process technology and manufacturing.

Technology Development presented by Ann Kelleher

Last year Intel presented their Intel Accelerated plan and, in this meeting, we got a review of where Intel stands on that… Read More


Samsung Keynote at IEDM

Samsung Keynote at IEDM
by Scotten Jones on 01-27-2022 at 6:00 am

Samsung Keynote Figure 1

Kinam Kim is a longtime Samsung technologist who has published many excellent articles over the years. He is now the Chairman of Samsung Electronics, and he gave a very interesting keynote address at IEDM.

He began with some general observations:

The world is experiencing a transformation powered by semiconductors that has been… Read More


IBM at IEDM

IBM at IEDM
by Scotten Jones on 01-10-2022 at 6:00 am

Vertical FET process

IBM transferred their semiconductor manufacturing to GLOBALFOUNDRIES several years ago but still maintains a multibillion-dollar research facility at Albany Nanotech. IBM is very active at conferences such as IEDM and appears to have a good public relations department because they get a lot of press.

At the Litho Workshop … Read More


Intel Discusses Scaling Innovations at IEDM

Intel Discusses Scaling Innovations at IEDM
by Scotten Jones on 12-14-2021 at 6:00 am

Intel at IEDM Slides Page 1

Standard Cell Scaling

Complex logic designs are built up from standard cells, in order to continue to scale logic we need to continually shrink the size of standard cells.

Figure 1 illustrates the dimensions of a standard cell.

 Figure 1. Standard Cell Dimensions.

 From figure 1 we can see that shrinking standard cell sizes requires… Read More


SISPAD – Cost Simulations to Enable PPAC Aware Technology Development

SISPAD – Cost Simulations to Enable PPAC Aware Technology Development
by Scotten Jones on 10-31-2021 at 10:00 am

Slide11

I was invited to give a plenary address at the SISPAD conference in September 2021. For anyone not familiar with SISPAD it is a premiere TCAD conference. This year for the first time SISPAD wanted to address cost and my talk was “Cost Simulations to Enable PPAC Aware Technology Development”.

For many years the standard in technology… Read More