Podcast EP362: An atomic layer in compute. A discussion of what can be built as graphene photonics scales with Cedric Huyghebaert

Podcast EP362: An atomic layer in compute. A discussion of what can be built as graphene photonics scales with Cedric Huyghebaert
by Daniel Nenni on 08-21-2026 at 2:00 pm
Categories: Black Semiconductor, Semiconductor

Daniel is joined by Dr. Cedric Huyghebaert, CTO of Black Semiconductor. Cedric is one of the world’s leading experts in the development and integration of 2D materials, particularly graphene, into industrial semiconductor manufacturing. With a PhD in Physics from KU Leuven and over 25 years at imec, Cedric built and led… Read More

August 5, 2026August 5, 2026

Imec Unlocks System-Level III-V Chiplet Integration on Si-CMOS with Advanced 300mm RF Silicon Interposer Platform

Imec Unlocks System-Level III-V Chiplet Integration on Si-CMOS with Advanced 300mm RF Silicon Interposer Platform
by Daniel Nenni on 08-05-2026 at 6:00 am
Categories: Chiplet

As wireless communication systems evolve toward 6G, satellite connectivity, advanced radar, and high-performance sensing applications, the integration of heterogeneous semiconductor technologies has become a critical challenge. Silicon CMOS remains the dominant platform for digital processing and system control,… Read More

May 19, 2026May 18, 2026

imec IC-Link and TSMC 3DFabric Alliance Expansion Signals New Era of System-Level Scaling

imec IC-Link and TSMC 3DFabric Alliance Expansion Signals New Era of System-Level Scaling
by Daniel Nenni on 05-19-2026 at 6:00 am
Categories: 3D IC, Chiplet, Semiconductor, TSMC

imec announced that IC-Link by imec has joined the TSMC 3DFabric Alliance, a strategically important move that reflects the semiconductor industry’s transition from traditional monolithic scaling toward heterogeneous integration, chiplet architectures, and advanced packaging-driven system optimization. The partnership… Read More

May 18, 2026May 18, 2026

Crossing the Yield Cliff: IDP V6 and the Future of Manufacturing Forecasting

Crossing the Yield Cliff: IDP V6 and the Future of Manufacturing Forecasting
by Admin on 05-18-2026 at 10:00 am
Categories: Lithography
4 Comments

The paper, Industrial Defectivity Prediction (IDP) V6: A Two-Layer Yield Cliff Framework for Cross-Industry Mass-Production Forecasting, presents a generalized industrial yield-modeling architecture that extends the classical Negative Binomial framework through a two-layer phenomenological structure designed … Read More

March 25, 2026March 24, 2026

Chemical Origins of Environmental Modifications to MOR Lithographic Chemistry

Chemical Origins of Environmental Modifications to MOR Lithographic Chemistry
by Daniel Nenni on 03-25-2026 at 10:00 am
Categories: Events, Lithography
1 Comment

In the pursuit of advanced extreme ultraviolet (EUV) lithography for high-NA patterning, metal oxide resists (MORs) offer significant promise but face challenges like critical dimension (CD) variation due to atmospheric interactions. Presented at SPIE Advanced Lithography + Patterning 2025 by Kevin M. Dorney and colleagues… Read More

March 23, 2026March 23, 2026

Beyond Moore’s Law: High NA EUV Lithography Redefines Advanced Chip Manufacturing

Beyond Moore’s Law: High NA EUV Lithography Redefines Advanced Chip Manufacturing
by Daniel Nenni on 03-23-2026 at 8:00 am
Categories: Lithography
1 Comment

The imec installation of the ASML EXE:5200 High Numerical Aperture (High NA) extreme ultraviolet (EUV) lithography system at imec represents a pivotal advancement in semiconductor manufacturing and research. This system, installed in imec’s 300 mm cleanroom in Leuven, Belgium, introduces unprecedented lithographic resolution… Read More

March 15, 2026March 18, 2026

Unraveling Dose Reduction in Metal Oxide Resists via Post-Exposure Bake Environment

Unraveling Dose Reduction in Metal Oxide Resists via Post-Exposure Bake Environment
by Daniel Nenni on 03-15-2026 at 4:00 pm
Categories: Events, Lithography
1 Comment

In the realm of extreme ultraviolet (EUV) lithography, metal oxide resists (MORs) have emerged as promising candidates for advanced semiconductor patterning. However, their stability poses challenges, particularly interactions with clean-room environments like humidity and airborne molecular contaminants (AMCs) … Read More

December 14, 2025December 16, 2025

imec on the Benefits of ASICs and How to Seize Them

imec on the Benefits of ASICs and How to Seize Them
by Daniel Nenni on 12-14-2025 at 2:00 pm
Categories: Semiconductor Services

In an era where product differentiation increasingly depends on performance, power efficiency, and form factor, Application-Specific Integrated Circuits (ASICs) have become the ultimate competitive weapon for innovative companies. Unlike off-the-shelf processors, FPGAs, or even ASSPs, a full- or semi-custom ASIC is… Read More

October 19, 2025October 20, 2025

CMOS 2.0 is Advancing Semiconductor Scaling

CMOS 2.0 is Advancing Semiconductor Scaling
by Daniel Nenni on 10-19-2025 at 10:00 am
Categories: 3D IC

In the rapidly evolving landscape of semiconductor technology, imec’s recent breakthroughs in wafer-to-wafer hybrid bonding and backside connectivity are paving the way for CMOS 2.0, a paradigm shift in chip design. Introduced in 2024, CMOS 2.0 addresses the limitations of traditional CMOS scaling by partitioning… Read More

October 10, 2025October 10, 2025

Exploring TSMC’s OIP Ecosystem Benefits

Exploring TSMC’s OIP Ecosystem Benefits
by Daniel Nenni on 10-10-2025 at 6:00 am
Categories: 3D IC, AI, Chiplet, EDA, Events, IP, Semiconductor, TSMC

Now that the dust has settled let’s talk more about TSMC’s Open Innovation Platform. Launched in 2008, OIP represents a groundbreaking collaborative model in the semiconductor industry. Unlike IDMs that controlled the entire supply chain, OIP fosters an “open horizontal” ecosystem uniting TSMC… Read More