VLSI Symposium 2020 – Imec Monolithic CFET

VLSI Symposium 2020 – Imec Monolithic CFET
by Scotten Jones on 09-13-2020 at 10:00 am

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The 2020 VLSI Technology Symposium was held as a virtual conference from June 14th through June 19th. At the symposium Imec gave an interesting paper on Monolithic CFET and I had a chance to interview one of the authors, Hiroaki Arimura.

It is well known in the industry that FinFETs (FF) are reaching the end of their scaling life. Samsung… Read More


SEMICON West – Applied Materials Selective Gap Fill Announcement

SEMICON West – Applied Materials Selective Gap Fill Announcement
by Scotten Jones on 08-17-2020 at 5:00 pm

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At SEMICON West, Applied Materials announced a new selective gap fill tool to address the growing resistance issues in interconnect at small dimensions. I had the opportunity to discuss this new tool and the applications for it with Zhebo Chen global product manager in the Metal Deposition Products group at Applied Materials.… Read More


Imec Technology Forum and ASML

Imec Technology Forum and ASML
by Scotten Jones on 07-30-2020 at 6:00 am

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On Thursday July 9 Imec held a virtual technology forum. Imec is one of the premier research organizations working on semiconductor technology and their forums are always interesting. My area of interest is process technology and the following are my observation in that area from the forum.

Luc Van Den Hove
Luc Van Den Hove is the… Read More


VLSI Symposium 2020 – Imec Buried Power Rail

VLSI Symposium 2020 – Imec Buried Power Rail
by Scotten Jones on 07-26-2020 at 10:00 am

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The 2020 VLSI Technology Symposium was held as a virtual conference from June 14th through June 19th. At the symposium Imec gave an interesting paper on Buried Power Rails (BPR) and I had a chance to interview one of the authors, Anshul Gupta.

As logic devices continue to scale down metal pitch is reaching a limit. Imec defines a pitch… Read More


Contact Resistance: The Silent Device Scaling Barrier

Contact Resistance: The Silent Device Scaling Barrier
by Fred Chen on 05-24-2020 at 6:00 am

Contact Resistance The Silent Device Scaling Barrier

Moore’s Law has been about device density, specifically transistor density, increasing every certain number of years. Although cost is the most easily grasped advantage, there are two other benefits: higher performance (speed) and reduced power. When these benefits are compromised, they can also pose a scaling limitation.

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Coronavirus Chops SPIE Litho EUV Conference

Coronavirus Chops SPIE Litho EUV Conference
by Robert Maire on 03-01-2020 at 6:00 am

SPIE EUV 2020 Coronavirus

Corona Curtails already quiet SPIE Litho conference
Our best guess is that attendance was off by 30% from last years SPIE conference due to a lack of travelers from many Asian areas obviously out of Corona fear. Even Intel, which is a few miles away was a virtual no-show with a mass cancellation.

More importantly, virtually all after… Read More


IEDM 2019 – Imec Interviews

IEDM 2019 – Imec Interviews
by Scotten Jones on 01-21-2020 at 6:00 am

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Imec is one of the premier semiconductor research organizations and at IEDM they presented dozens of papers. I had the opportunity to see several of the papers presented and interview 3 of Imec’s researchers.

Jan Van Houdt, DMTS ferroelectric and exploratory memory

I have had very interesting discussions with Imec researchers… Read More


Semicon West 2019 – Day 2

Semicon West 2019 – Day 2
by Scotten Jones on 07-18-2019 at 10:00 am

Tuesday July 9th was the first day the show floor was open at Semicon. The following is a summary of some announcements I attended and general observations.

AMAT Announcement

My day started with an Applied Materials (AMAT) briefing for press and analysts where they announced “the most sophisticated system they have ever released”.… Read More


SEMICON West 2019 – Day 1 – Imec

SEMICON West 2019 – Day 1 – Imec
by Scotten Jones on 07-15-2019 at 10:00 am

On Monday, July 8th Imec held a technology forum ahead of Semicon West. I saw the papers presented and interviewed three of the authors. The following is a summary of what I feel are the keys points of their research.

Arnaud Furnemont
Arnaud Furnemont’s talk was titled “From Technology Scaling to System Optimization”. Simple 2D … Read More


SPIE Advanced Lithography Conference – Imec and Veeco on EUV

SPIE Advanced Lithography Conference – Imec and Veeco on EUV
by Scotten Jones on 04-19-2019 at 12:00 pm

At the SPIE Advanced Lithography Conference Imec presented several papers on EUV and Veeco presented about etching for EUV masks. I had the opportunity to see the presentations and speak with some of the authors. In this article I will summarize the key issues around EUV based on this research.

EUV is ramping up into high volume 7nm… Read More