Access to advanced semiconductor technology involves much more than choosing a process node. Design teams also need computing capacity, compatible tools, secure technology access, and experienced support. IC-Link by imec’s expanded collaboration with TSMC addresses that combination, potentially making sophisticated… Read More
Tag: imec
Podcast EP362: An atomic layer in compute. A discussion of what can be built as graphene photonics scales with Cedric Huyghebaert
Daniel is joined by Dr. Cedric Huyghebaert, CTO of Black Semiconductor. Cedric is one of the world’s leading experts in the development and integration of 2D materials, particularly graphene, into industrial semiconductor manufacturing. With a PhD in Physics from KU Leuven and over 25 years at imec, Cedric built and led… Read More
Imec Unlocks System-Level III-V Chiplet Integration on Si-CMOS with Advanced 300mm RF Silicon Interposer Platform
As wireless communication systems evolve toward 6G, satellite connectivity, advanced radar, and high-performance sensing applications, the integration of heterogeneous semiconductor technologies has become a critical challenge. Silicon CMOS remains the dominant platform for digital processing and system control,… Read More
imec IC-Link and TSMC 3DFabric Alliance Expansion Signals New Era of System-Level Scaling
imec announced that IC-Link by imec has joined the TSMC 3DFabric Alliance, a strategically important move that reflects the semiconductor industry’s transition from traditional monolithic scaling toward heterogeneous integration, chiplet architectures, and advanced packaging-driven system optimization. The partnership… Read More
Crossing the Yield Cliff: IDP V6 and the Future of Manufacturing Forecasting
The paper, Industrial Defectivity Prediction (IDP) V6: A Two-Layer Yield Cliff Framework for Cross-Industry Mass-Production Forecasting, presents a generalized industrial yield-modeling architecture that extends the classical Negative Binomial framework through a two-layer phenomenological structure designed … Read More
Chemical Origins of Environmental Modifications to MOR Lithographic Chemistry
In the pursuit of advanced extreme ultraviolet (EUV) lithography for high-NA patterning, metal oxide resists (MORs) offer significant promise but face challenges like critical dimension (CD) variation due to atmospheric interactions. Presented at SPIE Advanced Lithography + Patterning 2025 by Kevin M. Dorney and colleagues… Read More
Beyond Moore’s Law: High NA EUV Lithography Redefines Advanced Chip Manufacturing
The imec installation of the ASML EXE:5200 High Numerical Aperture (High NA) extreme ultraviolet (EUV) lithography system at imec represents a pivotal advancement in semiconductor manufacturing and research. This system, installed in imec’s 300 mm cleanroom in Leuven, Belgium, introduces unprecedented lithographic resolution… Read More
Unraveling Dose Reduction in Metal Oxide Resists via Post-Exposure Bake Environment
In the realm of extreme ultraviolet (EUV) lithography, metal oxide resists (MORs) have emerged as promising candidates for advanced semiconductor patterning. However, their stability poses challenges, particularly interactions with clean-room environments like humidity and airborne molecular contaminants (AMCs) … Read More
imec on the Benefits of ASICs and How to Seize Them
In an era where product differentiation increasingly depends on performance, power efficiency, and form factor, Application-Specific Integrated Circuits (ASICs) have become the ultimate competitive weapon for innovative companies. Unlike off-the-shelf processors, FPGAs, or even ASSPs, a full- or semi-custom ASIC is… Read More
CMOS 2.0 is Advancing Semiconductor Scaling
In the rapidly evolving landscape of semiconductor technology, imec’s recent breakthroughs in wafer-to-wafer hybrid bonding and backside connectivity are paving the way for CMOS 2.0, a paradigm shift in chip design. Introduced in 2024, CMOS 2.0 addresses the limitations of traditional CMOS scaling by partitioning… Read More
