On Monday morning at IEDM, Sri Samavedam of Imec opened the technical program with a plenary talk entitled “Future Logic Scaling: Towards Atomic Channels and Deconstructed Chips”. I am not generally a fan of plenary talks, I think the presenters often try to cover too much in their talks and end up not providing enough detail to be… Read More
The 2020 VLSI Technology Symposium was held as a virtual conference from June 14th through June 19th. At the symposium Imec gave an interesting paper on Monolithic CFET and I had a chance to interview one of the authors, Hiroaki Arimura.
It is well known in the industry that FinFETs (FF) are reaching the end of their scaling life. Samsung… Read More
At SEMICON West, Applied Materials announced a new selective gap fill tool to address the growing resistance issues in interconnect at small dimensions. I had the opportunity to discuss this new tool and the applications for it with Zhebo Chen global product manager in the Metal Deposition Products group at Applied Materials.… Read More
On Thursday July 9 Imec held a virtual technology forum. Imec is one of the premier research organizations working on semiconductor technology and their forums are always interesting. My area of interest is process technology and the following are my observation in that area from the forum.
Luc Van Den Hove
Luc Van Den Hove is the… Read More
The 2020 VLSI Technology Symposium was held as a virtual conference from June 14th through June 19th. At the symposium Imec gave an interesting paper on Buried Power Rails (BPR) and I had a chance to interview one of the authors, Anshul Gupta.
As logic devices continue to scale down metal pitch is reaching a limit. Imec defines a pitch… Read More
Moore’s Law has been about device density, specifically transistor density, increasing every certain number of years. Although cost is the most easily grasped advantage, there are two other benefits: higher performance (speed) and reduced power. When these benefits are compromised, they can also pose a scaling limitation.
Corona Curtails already quiet SPIE Litho conference
Our best guess is that attendance was off by 30% from last years SPIE conference due to a lack of travelers from many Asian areas obviously out of Corona fear. Even Intel, which is a few miles away was a virtual no-show with a mass cancellation.
More importantly, virtually all after… Read More
Imec is one of the premier semiconductor research organizations and at IEDM they presented dozens of papers. I had the opportunity to see several of the papers presented and interview 3 of Imec’s researchers.
Jan Van Houdt, DMTS ferroelectric and exploratory memory
I have had very interesting discussions with Imec researchers… Read More
Tuesday July 9th was the first day the show floor was open at Semicon. The following is a summary of some announcements I attended and general observations.
My day started with an Applied Materials (AMAT) briefing for press and analysts where they announced “the most sophisticated system they have ever released”.… Read More
On Monday, July 8th Imec held a technology forum ahead of Semicon West. I saw the papers presented and interviewed three of the authors. The following is a summary of what I feel are the keys points of their research.
Arnaud Furnemont’s talk was titled “From Technology Scaling to System Optimization”. Simple 2D … Read More