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Imec Buried Power Rail and Backside Power Delivery at VLSI

Imec Buried Power Rail and Backside Power Delivery at VLSI
by Scotten Jones on 06-28-2022 at 6:00 am

At the VLSI Technology Symposium Imec presented on Buried Power Rails (BPR) and Backside Power Delivery (BSPD) in a paper entitled: “Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails”. I recently had a chance to interview one of the authors, Naoto Horiguchi about the work. I have interviewed Naoto several times in the past and presented alongside him at conferences and I always enjoy our conversations, he is very knowledgeable and easy to talk to.

Power Delivery is a growing problem at the leading edge. Two key issues addressed in this work are:

  1. On the metal 2 level there are power and ground rails at the top and bottom of standard logic cells. These rails are wider than routing lines to minimize the IR drop. Because half of each line is in the standard cell the wide lines limit cell scaling. As we transition to nanosheets this issue must be addressed to get to cells with less than 6-tracks.
  2. The upper metal layers of a process are very wide and provide global routing of power, but with 16 or more metal layers becoming common, there is a big IR drop bringing the power down through the chain of vias between each metal layer.

In this work the first problem is addressed with BPR, BPR replaces wide-thin power rails in metal 2, with tall-narrow power rails buried in the substrate. This technique reduces the area lost at the cell boundaries and for nanosheets can enable a 5-track or smaller cell.

The second piece is BSPD where the global power routing is done on the back of the wafer and then routed through the wafer with nano-Through Silicon Vias (nTSV). In order to minimize the IR drop the wafer must be very thin and the impact of extreme wafer thinning on the devices is explored in this work.

Figure 1 summarizes the scenarios:

Imec BPR Page 06

Figure 1. Power Delivery Scenarios.

The addition of BPR reduces the dynamic IR drop by 26% and the addition of BSPD improves the IR drop by an additional 75%, see figure 2.

Imec BPR Page 08

Figure 2. Dynamic Power Drop.

 Static IR drop is reduced by 23% by BPR and an additional 95% by adding BSPD, see figure 3.

Imec BPR Page 10

Figure 3. Static Power Drop.

In previous BPR work Imec has used Ruthenium (Ru) for the BPR metal but in this work, they used Tungsten (W). Naoto said that Ru will be necessary at some point to support further scaling but at the scale of this work W was fine and is a well known metal in fabrication with well-defined cleans.

In figure 4, cross sections of the resulting structure and connections are shown. What I find amazing in this work is how incredibly thin the wafer is at less than one-micron. This enables low resistance for the nTSV.

BPR Page 12

Figure 4. Cross Section and Device Connections.

In figure 5 the process is illustrated for BPR and BSPD.

BPR Page 14

Figure 5. BPR and BSPD Process.

Some comments about the process flow:

  • An epitaxial process is used to deposit a silicon-germanium (SiGe) layer used as an etch-stop layer and then on top of that the silicon device layer is formed.
  • The W BPR is formed in the wafer.
  • The devices are fabricated.
  • The wafer is bonded to a carrier wafer.
  • Backgrind followed by a wet etch stopping on the SiGe layers is used to thin the wafer.
  • nTSVs are formed.
  • The BSPD is formed.
  • The wafer is annealed to recover performance.

I asked Naoto about the material used to bond the wafers together because the BSPD temperatures are likely too high for most temporary bonding materials. He said a Chemical Vapor Deposited (CVD) dielectric is used. This is based on the wafers not being separated after the process, this means signal lines would have to be routed in from the backside along with power.

Authors note: another question I recently looked into is how you precisely align the nTSV to the front side so they land on the BPR. I had a conversation with a contact at ASML and they said with the wafer this thin the aligners can “see” the front side alignment marks through the wafer. There are some distortion issues, but they are manageable. Long term there is interest in landing nTSV right on source/drains and that will require more work on alignment accuracy.

The bulk of this work was to evaluate device performance and the impact of extreme wafer thinning on the devices. Naoto said in some tests they thinned wafers until they hit the shallow trench isolation and they still got good device performance after annealing the wafer.

Authors note, both Intel and TSMC have announced BSPD for 2nm generation processes, clearly that is an emerging technology.

I told Naoto my sense is companies are hesitant to implement BPR because they must embed metals in the wafer prior to device formation. Intel has announced their BSPD with TSV’s they call PowerVia, they do not use BPR at least for their 20A and 18A process. TSMC is less clear to me, but I think they are avoiding BPR also. Naoto said he thought it wouldn’t be used in first generation BSPD but should be considered for further scaling.

This paper didn’t cover this, but BSPD also offers the possibility to add more functionality to the back of the wafer such as ESD devices, MIM capacitors, etc.

In conclusion, Imec has shown that BPR and BSPD can address the power delivery IR drop problem without degrading devices. This is important work for continued logic scaling.

Also read:


The Lost Opportunity for 450mm

Intel and the EUV Shortage

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