Samsung and TSMC have both made recent disclosures about their 5nm process and I though it would be a good time to look at what we know about them and compare the two processes.
A lot of what has been announced about 5nm is in comparison to 7nm so we will first review 7nm.
Figure 1 compares Samsung’s 7LPP process to TSMC’s 7FF and 7FFP processes. The rows in the table are:
- Company name
- Process name
- M2P – metal 2 pitch, this is chosen because M2P is used to determine cell height
- Tracks – the number of metal two pitches in the cell height
- Cell height – the M2P x Tracks
- CPP – contacted polysilicon pitch
- DDB/SDB – double diffusion break (DDB) or single diffusion break (SDB). DDB requires an extra CPP in width at the edge of a standard cell
- Transistor density – this is uses the method popularized by Intel that I have written before where two input NAND cell size and scanned flip flop cell sizes are weighted to give a transistors per millimeter metric
- Layers – this is the number of EUV layers over the total number of layers for the process
- Relative cost – using Samsung’s 7LPP cost as the baseline we compare the normalized cost of each process to 7PP. The cost values were calculated using the IC Knowledge – Strategic Cost Model – 2019 – revision 01 versions for a new 40,000 wafers per month wafer fabs in either South Korea for Samsung or Taiwan for TSMC
Figure 1. 7nm comparison
Looking at figure 1 it is interesting to note that Samsung’s 7LPP process is less dense than either of TSMC’s processes in spite of using EUV and having the smallest M2P. TSMC more than makes up for Samsung’s tighter pitch with a smaller track height and then for 7FFP a SDB. For TSMC 7FF without EUV moving to 7FFP with EUV reduces the mask count and adds SDB improving the density by 18%.
Now that we have a solid view of 7nm we are ready to look forward to 5nm:
Both Samsung and TSMC have started taking orders for 5nm with risk production this year and high-volume production next year. We expect both companies to employ more EUV layers at 5nm with 12 for Samsung and 14 for TSMC.
Samsung has said their 5nm process offers a 25% density improvement over 7nm with a 10% performance boost or 20% lower power consumption. My understanding is the difference between 7LPP and 5LPE for Samsung is a 6-track cell height and SDB. This results in a 1.33x density improvement.
This contrasts with TSMC who announced a 1.8x density improvement and a 15% performance improvement or 30% lower power. I recently saw another analyst claim that Samsung and TSMC would have similar density at 5nm, that one really left me scratching my head given that the two companies have similar 7nm density and TSMC has announced a much larger density improvement than Samsung. My belief is that TSMC will have a significant density advantage over Samsung at 5nm.
Figure 2 summarizes the two processes using the same metrics as figure 1 with the addition of a density improvement versus 5nm row.Figure 2. 5nm comparison
From figure 2 you can see that we expect TSMC to have a 1.37x density advantage over Samsung with a lower wafer cost!
Another interesting item in this table is TSMC reaching 30nm for M2P. We have heard they are being aggressive on M2P with numbers as low as 28nm mentioned. We assumed 30nm as a slight relaxation from the 28nm number to produce the 1.8x density improvement, TSMC had at one time said 5nm would have a 1.9x density improvement.
We believe TSMC’s 5nm process will significantly outperform Samsung’s 5nm process in all key metrics and represent the highest density logic process in the world when it ramps into production next year.
For more information on TSMC’s leading edge logic processes I recommend Tom Dillinger’s excellent summary of TSMC’s technology forum available here.