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SPIE 2017: EUV Readiness for High Volume Manufacturing

SPIE 2017: EUV Readiness for High Volume Manufacturing
by Scotten Jones on 03-03-2017 at 12:00 pm

The SPIE Advanced Lithography Conference is the world’s leading conference addressing photolithography. This year on the opening day of the conference, Samsung and Intel presented papers summarizing the readiness of EUV for high volume manufacturing (HVM). In this article, I will begin by summarizing the EUV plans of the four leading logic producers, I will then touch on some general observations over several years of the conference, I will discuss the Samsung and Intel papers, some additional observations and then conclude with the prospects for EUV in HVM.

Leading edge logic companies plans for EUV insertion
In 2016 Samsung and TSMC both began ramping up 10nm foundry processes, I am referring to them as “foundry” processes because the pitches are relaxed from what we would consider classic 10nm node processes. Both processes are produced with optical lithography and are currently the densest logic processes in production. For TSMC, 10nm is expected to be a short-lived node primarily focused on cell phone applications processors. For Samsung 10nm will likely be a longer-lived node for reasons discussed below.

In 2017 we expect to see TSMC ramp up a 7nm foundry node and Intel to ramp up a 10nm node process. Based on our current understanding, we expect the pitches for TSMC’s 7nm foundry process and Intel’s 10nm process to be identical. There is some evidence that Intel’s 10nm process may have a smaller track height than TSMC’s 7nm process possibly resulting in Intel’s 10nm process being denser than TSMC’s 7nm process. The preceding sentence points out how little the node names companies assign to their processes mean today. Both TSMC’s foundry 7nm process and Intel’s 10nm process will be produced with optical lithography although TSMC will be using 7nm as a EUV test vehicle.

In 2018 we expect foundry 7nm processes from GLOBALFOUNDRIES and Samsung. The GLOBALFOUNDRIES process will initially be produced with optical lithography but when EUV is ready they will offer EUV (in fact they are currently using EUV to speed up development of the process), Samsung has announced their 7nm foundry process will be produced with EUV. Samsung’s bet on EUV adds some uncertainty to their late 2018 process launch date and means their 10nm node will be a longer-lived node for them.

In 2019 we expect TSMC to begin ramping their 5nm foundry process and we expect this process to use EUV. Around 2020 we would expect Intel to introduce their 7nm process and assuming EUV readiness, we would expect Intel to use EUV for this process.

General observations on EUV at SPIE

I have been attending the SPIE Advanced Lithography Conference for many years. In 2014 TSMC gave a very pessimistic assessment of EUV and I would describe the overall conference “mood’ as being EUV pessimistic. In 2015 and 2016 I, would describe the EUV mood as being more hopeful including more upbeat assessments of EUV from TSMC. In 2017 I would once again describe the conference mood as optimistic on EUV although TSMC did not present an assessment this year and I have heard TSMC is currently less optimistic than some others. I also saw less momentum behind alternative techniques such as directed self-assembly.

Another observation that I think is very interesting, in the past EUV was viewed as a technology that had to be less expensive than optical to be introduced. Now I believe that the attitude is that we need EUV for other reasons and it only needs be reasonably economical to be implemented. Specifically, I believe there is a growing realization that we cannot live with the rising masks counts at the leading edge and the impact of high mask counts on cycle time and yield. Also, complex multi-patterning schemes add deposition and etch tools to the process flow that are squeezing out other equipment and reducing fab capacity at each new node. The promise of EUV is reduced mask counts, better pattern fidelity and higher and more consistent electrical yield.

Samsung and Intel papers
In the Intel paper, it was noted that in 2015 there were 7 EUV systems in the field, today there are 14 systems in the field split between 8 – NXE3300B systems and 6 – NXE3350B. As an industry, we are getting a lot more data and the NXE3350B is expected to be similar to the NXE3400. Samsung noted the advantages of EUV are higher pattern fidelity and a smaller number of masks noting that 7nm with EUV can be less masks than optical 10nm.

Intel noted that at the fall ASML symposium, ASML showed 210 watts and >125wph and they need to insure does control at high power. Source power in the field is lower but the NXE3400 systems are expected to close the gap. Samsung had a similar message noting significant source power progress approaching the HVM goal. The NXE3350B is showing steady 130-watt power.

Both Intel and Samsung discussed system availability, droplet generator and collector lifetime were focuses. Droplet generator lifetime is up over 3-5X from last year and collector lifetime is up 1.5x but both need more improvement. Overall system availability was reported to be 70% last year with high variability. Today Intel reports NXE3350B availability >75% and less extra-long down time events (authors note, as a former manufacturing manager, long down time events are particularly disruptive to the manufacturing line). Samsung noted NXE3350 has better predictability than the NXE3300.

Both Samsung and Intel noted that added defect levels were much higher in their measurements than in ASML’s measurements and both highlighted the need for pellicles. A pellicle concept was realized by ASML in early 2016. Pellicle shipments are now underway and pellicles have reached zero printable defects. Intel noted that with the current pellicle >3,500 wafers have been exposed with no added defects. The big concerns in pellicles now are the ramp up to production volumes and longer term new pellicle materials will be needed as source power increases above 250 watts. Samsung has implemented Actinic mask review using their own in-house system and it is now good enough for 7nm, Intel noted that Actinic mask inspection is still needed.

Samsung reported mask blank defects are now reaching the HVM goal of <5. This is a big improvement, last year at SEMICON West mask blank defects were limiting EUV usage to only dark field masks with low open area.

Per Intel, photoresist won’t gate introduction of EUV but better stochastics are needed that match 193. Samsung noted that resist performance is OK for 7nm but needs more sensitivity. Intel also mentioned that ASML has introduced a membrane between the wafer stage and the optics and that opens up new material options for photoresist because it protects the optics from photoresist out gassing. I was surprised that there wasn’t more discussion of line width roughness (LWR), my impression is LWR is the big unsolved issue of EUV. In discussions with various experts over the rest of the conference I was told that at 7nm initial EUV use will be for vias and they are less sensitive to LWR but that improvement is definitely needed for 5nm. I will discuss photoresist and work on LWR smoothing more in follow on SPIE blogs.

Other observations
Two other interesting discussions I had on EUV at the conference:

I had a discussion on how the delay in EUV has given the technology time to mature and the industry to prepare. I used to produce a model of the industry-wide demand for process tools by tool type that accounted for node transition and new technology introductions. When EUV was going to replace multi-patterning as a single exposure technology my modeling showed a few years of very high etch and deposition system requirements from the OEMs and then a big drop off. That always struck me as a big issue for the OEMs. Today EUV is poised to slowly ramp into the industry as a more complementary technology and not disrupt the rest of the OEM infrastructure. This may be the one silver lining to the EUV delay.

As a cautionary note, in another discussion I heard that there may be some evidence of decay in the EUV system optics over time, not just the collector. If true this would be a big problem.

To summarize the two talks the following are the key points:

* Source power – HVM levels demonstrated but needs to be seen in the field.
* Availability – improving but needs to improve faster.
* Pellicle – looks good for now but needed in production.
* Masks – good progress but actinic inspection needed.
* Resist – good enough for initial 7nm use but need more sensitivity and better LWR.

Based on everything I saw and heard at the conference I am cautiously optimistic that we will start to see EUV in manufacturing use on selected levels late 2018 with wider adoption in 2019. I would expect the broadest use at Samsung in late 2018 followed by GLOBALFOUNDRIES. I don’t expect TSMC or Intel to begin to use EUV until 2019 and 2020 respectively.

In terms of roll out my expectation is:
* Vias/contacts – single exposure – late 2018.
* Metal – ideally a single EUV exposure but depending on LWR progress may be SAQP with EUV block – late 2018/early 2019.
* FEOL – SAQP with EUV cuts, only makes sense when several cut masks are needed. Likely a 2019/2020 usage.

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