EUV faces Scylla and Charybdis

EUV faces Scylla and Charybdis
by Fred Chen on 08-03-2020 at 6:00 am

EUV faces Scylla and Charybdis

It is now time for the EUV community to realize they are caught between the proverbial Scylla and Charybdis. In Greek mythology, the two monsters terrorized ships that were unlucky enough to pass between them. By avoiding one, you approached the other.

S for Scylla, or Stochastics

Scylla was a former beautiful nymph turned into

Read More

Application-Specific Lithography: a 28 nm Pitch DRAM Active Area

Application-Specific Lithography: a 28 nm Pitch DRAM Active Area
by Fred Chen on 07-19-2020 at 2:00 pm

Application Specific Lithography 28 nm Pitch DRAM Active Area

In the recent DRAM jargon, “1X”, “1Y”, “1Z”, etc. have been used to express all the sub-20 nm process generations. It is almost possible now to match them to real numbers which are roughly the half-pitch of the DRAM active area, such as 1X=18, 1Y ~ 17, etc. At this rate, 14 nm is somewhere around

Read More

ASML More Covid Concerns and Impact

ASML More Covid Concerns and Impact
by Robert Maire on 07-19-2020 at 6:00 am

ASML Covid
  • Covid related Revenue Rec causes rev/EPS miss
  • Sharp order drop reflects H2 industry uncertainty
  • EUV remains solid- Memory/Logic mix is better

Results were in line after correcting Covid Caused Revenue Rec issue-
ASML reported revenues of Euro3.3B and EPS of Euro1.79 as revenues from two EUV systems was not recognized, due to … Read More


Application-Specific Lithography: The 5nm 6-Track Cell

Application-Specific Lithography: The 5nm 6-Track Cell
by Fred Chen on 07-05-2020 at 10:00 am

Application Specific Lithography The 5nm 6 Track Cell

The 5nm foundry (e.g., TSMC) node may see the introduction of 6-track cells (two double-width rails plus four minimum-width dense lines) with a minimum metal pitch in the neighborhood of 30 nm. IMEC had studied a representative case as its ‘7nm’ case [1]. TSMC had some published 5nm test structures which looked like… Read More


The Stochastic Impact of Defocus in EUV Lithography

The Stochastic Impact of Defocus in EUV Lithography
by Fred Chen on 06-28-2020 at 6:00 am

The Stochastic Impact of Defocus in EUV Lithography

The stochastic nature of imaging has received a great deal of attention in the area of EUV lithography. The density of EUV photons reaching the wafer is low enough [1] that the natural variation in the number of photons arriving at a given location can give rise to a relatively large standard deviation.

In recent studies [2,3], it … Read More


The Uncertain Phase Shifts of EUV Masks

The Uncertain Phase Shifts of EUV Masks
by Fred Chen on 05-13-2020 at 10:00 am

The Uncertain Phase Shifts of EUV Masks

EUV (Extreme UltraViolet) lithography has received attention within the semiconductor industry since its development inception in 1997 with the formation of the EUV LLC [1], and more recently, since the 7nm node began, with limited use by Samsung and TSMC being touted as key advantages [2, 3]. As with any key critical technology,

Read More

Covid Created Collateral China Crisis

Covid Created Collateral China Crisis
by Robert Maire on 05-03-2020 at 6:00 am

China US Trade Agreement 2020

Economic damage-
China relationship damage will far outlast direct Covid19 logistics impact-
Economic damage could be huge but trade damage could be larger with more specific impact on chips-

A long build up to a China trade nuclear winter, the “drum-beat of war”
When we started talking about a potential chip trade… Read More


ASML A Scenario More Lumpy While Demand and Tech Remain Solid Despite Covid Delays

ASML A Scenario More Lumpy While Demand and Tech Remain Solid Despite Covid Delays
by Robert Maire on 04-22-2020 at 2:00 pm

ASML SemiWiki 2020

Covid issues create “lumpy” quarters due to delays
Orders & demand remain solid and strong
2020 Year financials intact so far but ignore Qtrs
Taking prudent actions- no buybacks or guidance

As expected, Covid impacts both shipments & supply chain, ignore the near term lumpiness…
ASML reported revenues… Read More


SPIE 2020 – ASML EUV and Inspection Update

SPIE 2020 – ASML EUV and Inspection Update
by Scotten Jones on 04-20-2020 at 10:00 am

0.33 NA EUV systems for HVM Ron Schuurhuis Page 02

I couldn’t attend the SPIE Advanced Lithography Conference this year for personal reasons, but last week Mike Lercel of ASML was nice enough to walk me through the major ASML presentations from the conference.

Introduction
In late 2018, Samsung and TSMC introduced 7nm foundry logic processes with 5 to 7 EUV layers, throughout … Read More


Lithography Resolution Limits – Arrayed Features

Lithography Resolution Limits – Arrayed Features
by Fred Chen on 04-17-2020 at 6:00 am

Lithography Resolution Limits Arrayed Features

State-of-the-art chips will always include some portions which are memory arrays, which also happen to be the densest portions of the chip. Arrayed features are the main targets for lithography evaluation, as the feature pitch is well-defined, and is directly linked to the cost scaling (more features per wafer) from generation… Read More