TSMC’s A16 technology, presented as Paper T1.5 at the June 2026 IEEE/JSAP VLSI Symposium, marks the company’s first angstrom-class CMOS platform combining enhanced nanosheet gate-all-around transistors with backside power delivery. The key integration feature is Super Power Rail, or SPR, which TSMC describes as a backside… Read More
At the 2026 VLSI Symposium, Intel Foundry provided a detailed update on its process technology roadmap, highlighting the continued maturation of Intel 18A, the introduction of Intel 18A-P, and several advanced research initiatives that extend beyond current gate-all-around (GAA) transistor architectures. The presentation… Read More
Dan is joined by Dr. Tahir Ghani, Intel senior fellow and director of process pathfinding in Intel’s Technology Research Group. Tahir has a 30-year career at Intel working on many innovations, including strained silicon, high-K metal gate devices, FinFETs, RibbonFETs, and backside power delivery (BSPD), among others. He has… Read More
At the VLSI Technology Symposium Imec presented on Buried Power Rails (BPR) and Backside Power Delivery (BSPD) in a paper entitled: “Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails”. I recently had a chance to interview one of the authors, Naoto Horiguchi about the work. I have interviewed … Read More
