Intel Foundry Expands the 18A Platform with 18A-P and Demonstrates Long-Term Technology Leadership at VLSI 2026

At the 2026 VLSI Symposium, Intel Foundry provided a detailed update on its process technology roadmap, highlighting the continued maturation of Intel 18A, the introduction of Intel 18A-P, and several advanced research initiatives that extend beyond current gate-all-around (GAA) transistor architectures. The presentation underscored Intel’s strategy of combining manufacturing execution with differentiated process technologies to strengthen its position in the foundry market.

The absolute best slide from the pre-briefing was the first one above. This insight comes directly from Lip-Bu Tan and his experience at Cadence, working closely with TSMC and the world’s leading semiconductor companies.

It is a shame that Samsung Foundry has not fully embraced this approach as well. The recipe is actually quite simple: tell customers what you are going to do, do it, and then tell customers what you have done.

Anyone who has attended a TSMC Technical Symposium has seen this playbook in action. TSMC consistently communicates a clear roadmap, executes against it, and then returns to demonstrate measurable results. That discipline and transparency are a big part of why customers trust TSMC and continue to invest in its ecosystem.

Intel reported that its 18A process is now ramping in two U.S. fabrication facilities, with defect density continuing to decline ahead of internal projections. The company indicated that Intel 18A is already powering multiple client products, with data center applications expected to follow. This progress is significant because Intel 18A represents the company’s first production node integrating RibbonFET gate-all-around transistors and PowerVia backside power delivery, two technologies widely viewed as critical enablers for advanced logic scaling.

A major announcement at VLSI 2026 was Intel 18A-P, the first performance-enhanced derivative of the Intel 18A family. Unlike a simple process shrink, 18A-P introduces new transistor options, improved power delivery structures, and enhanced thermal characteristics while maintaining backward compatibility with existing Intel 18A designs.

The process offers measurable improvements in power, performance, and area (PPA). Intel reported up to 18% lower power consumption at iso-performance and approximately 9% higher performance at iso-power based on a fully routed Arm core test vehicle. Additional enhancements include 20-40% improvements in thermal resistance and 10-30% lower via resistance on performance-critical interconnect layers.

One of the most notable innovations in Intel 18A-P is the introduction of a dual-contact Power Boost structure. This approach combines traditional front-side contacts with direct backside contacts enabled through PowerVia technology. By reducing parasitic resistance and improving current delivery, Intel can achieve higher transistor drive strength while simultaneously improving energy efficiency.

Intel also expanded the available threshold-voltage (Vt) options. A new intermediate Vt category positioned between Ultra-Low Vt (ULVT) and Low Vt (LVT) provides circuit designers with additional flexibility when balancing leakage power against performance. The company noted a 33% tightening of skew corners and reduced process variation, enabling more predictable timing closure and design optimization.

Thermal management was another focus area. Intel 18A-P incorporates both design and materials innovations aimed at improving heat dissipation. Enhanced thermal conductivity and advanced EDA-driven thermal optimization techniques are intended to support increasingly power-dense compute workloads, particularly in artificial intelligence and high-performance computing applications.

The symposium also featured new quantitative data regarding the advantages of combining Backside Power Delivery (BSPD) with Gate-All-Around transistors. Intel reported approximately 10× dynamic voltage droop reduction and 5-6% frequency improvements, or alternatively more than 15% dynamic power reduction. Additional benefits include routing simplification, improved area efficiency, and better translation of transistor-level performance gains into actual circuit-level frequency improvements.

Looking beyond current production technologies, Intel presented several advanced research projects. Among them was the development of Complementary FETs (CFETs), which stack PMOS and NMOS devices vertically to extend transistor density scaling beyond conventional GAA structures. Intel demonstrated a monolithic CFET inverter with a contacted poly pitch of 45 nm, highlighting progress toward future logic generations.

The company also showcased a ruthenium-based interconnect architecture featuring air-gap integration. This approach achieved approximately 35% capacitance reduction compared with traditional copper-based interconnects, potentially enabling higher operating frequencies while reducing signal delay and power consumption.

Another research highlight involved the integration of gallium nitride (GaN) power devices with silicon CMOS logic on 300 mm wafers. By combining power management and logic control on a single die, Intel aims to improve system efficiency while reducing packaging complexity and overall solution cost.

Bottom line: Collectively, these announcements demonstrate Intel Foundry’s dual focus on near-term manufacturing execution and long-term technology innovation. With Intel 18A entering production, 18A-P advancing performance capabilities, and a robust research pipeline spanning CFETs, advanced interconnects, and heterogeneous integration, Intel continues to position itself as a leading developer of next-generation semiconductor process technologies.

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